SU1397925A1 - Device for interfacing computer with peripheral device - Google Patents

Abstract

The invention relates to computer technology and can be used in interface devices of external equipment, which has input data in serial format with a computer channel. The aim of the invention is to reduce equipment. The device contains a register-receiver, a register-transmitter, a buffer register, two information rewriting blocks, a readiness shaping unit, a control block, a control signal register, and three triggers. 4 hp f-ly, 9 ill.

Description

co co vi

; about tc ate

The invention relates to computer technology and can be used in interface devices of external equipment, which has input data in serial format with a computer channel.

The purpose of the invention is to reduce equipment.

Figure 1 shows the block diagram of the device; figure 2 - block diagram. the second block rewriting; FIG. 3 is a block diagram of a first rewriting unit; figure 4 is a block diagram of the control unit

trigger 4 (figure 1); 60 - at the first input element And 31 (figure 4), the signal is Ready; 61 - at the output of the counter 39, overflow pulses; 62 - at the serial output of the register-transmitter 3 (Fig. 1, 6); 63 — tracking pulses (ICs) (FIG. 4) {64 — at the first control input of the register-transmitter 3, shifting pulses; 65 - at the fault input of the register-transmitter 3; 66 - at the first input of the element OR 29 (FIG. 4), reading pulse; 67 - on the sequential input reg

neither) in FIG. 3, a block diagram of the block for-15 of the country of receiver 1, and, in addition, an awesome readiness; Figures 6 and 7 are time diagrams of the recording mode of the device; Figures 8 and 9 are temporary dilgrams of the reading mode of the device.

The device (Fig. 1) contains a register-receiver-receiver 1, the first trigger 2, the register-transmitter 3, the third trigger 4, the second information rewriting unit 5, the external device (WU) 6, the buffer register 7, the second trigger 8 , 25, the first information rewriting unit 9, the control signal register 10, the readiness generation unit 11, the control unit 12 and the input group 13.

The second block 5 rewrites its information-30 to zero. From the first output of the block days (FIG. 2) contains elements 14 and 15 12 the signal also arrives at the set delay times and the number of the delay element (for example, 4i)

The device works as follows.

The device is reset by a Reset signal, which goes to one of the three buses of a group of inputs 13 of control unit 12 (Figures 1 and 4), flips the counter 39, passes through the OR element 29 and the delay element 42 resets the transmitter 3 and, having passed through the delay element 43, enters the zero input of the third trigger 4 and resets

delay, one-shot 16, elements

11PI 17-19.

The first block 9 of information rewriting (FIG. 3) contains OR elements 20 and 21, delay elements 22-24, and a single vibrator 25.

Control unit 12 (FIG. 4) contains OR elements 26-29, AND elements 30-38, counter 39, delay elements 40-43, AND element 44, OR element 45, delay element 46.

Block 11 forming readiness (figure 5) contains the elements And 47-49, the element OR 50, triggers 51 and 52.

In FIGS. 6-9, the pulses are indicated: 53 - at the first input of the element OR 26 1 (FIG. 4), the recording pulse; 54 - at the parallel output of the register-receiver 1 (FIG. 1), the presence or absence of information; 55 - at the single output of the trigger 2 (FIG. 1); 56 - at the parallel output of the buffer register 7 (figure 1), the presence or absence of information-, 57 - at the single output of the trigger 8 (figure 1); 58 - at the parallel output of the register-transmitter 3 (figure 1), the presence or absence of information; 59 - single output

delay times and the number of the delay element (for example, 4i)

The device works as follows.

The device is reset by a Reset signal, which goes to one of the three buses of the input group 13 of the control unit 12 (Figures 1 and 4), flips the counter 39, passes through the OR element 29 and the delay element 42 resets the transmitter register 3 and, having passed through the delay element 43, enters the zero input of the third trigger 4 and resets

The initial input of the second rewriting unit 5 (FIG. 2) passes through the OR element 17 and resets the trigger 8, passes through the OR element 18 and embraces the buffer register 7, then goes to the installation input of the first rewriting unit 9 (FIG. 3), goes through the elements OR 20 and 21 and resets

0, respectively, the first trigger 2 and the register-receiver 1. Then, the Reset signal is fed to the installation input of block 11 (FIG. 5) and resets the triggers 51 and 52.

5 In the initial state, on all input buses there are no enabling signals, the state of the register 10 control signals is not significant.

To implement the write mode to the corresponding register bit 10

0

five

(Fig. 1) is recorded 1, from the output of this discharge, the resolving potential is fed to the second input of the And 37 element (Fig. 4).

The absence of resolving potentials at the first inputs of the elements And 34 and 37 and at the inputs of the element And 31 creates conditions to which the corresponding potentials from the output of the element And 31 and

element OR 28, acting on the inputs of registers 1 and 3, set them to record mode. Then, the overhead word is recorded, which is fed to the parallel input of the register-receiver 1. A write pulse 53 (FIG. 6) is fed to the corresponding bus of the input group 13 of the control unit 12,

passes through the element OR 26 and, is rewritten to free

stupid to the control input of the register-receiver 1, records the service word (pulse 54, FIG. 6).

The write pulse from the output of the element OR 27 is delayed by the element 41 for the duration of the transient processes in register 1 and arrives at the single input of the trigger 2, setting it to a single state (pulse 55,

6). Allowing potentials with a unit of 20 units in the discharge register 10, the main output of trigger 2 and zero output of trigger 8 trigger the one-channel 25 (FIG. 3). The impulse from the output of the one-shot 25 is backed up by the eleating record mode (PZ), it is a necessary and sufficient condition for generating a signal. The beginning of the exchange (BUT), which determines) the output 24, at the end of the transition of the data array of register 7 and, entering it, records the service word from register 1 (pulse 56, FIG. 6).

This pulse is then delayed by element 23 for the duration of the pulse, passes through element OR 20, resets trigger 2 to the zero state, after which it is delayed by element 22 for the time it takes to set trigger 2 to zero and sets trigger 8 to one state (pulse 57 ), further, the passage through the element OR 21, resets the register-receiver 1.

Allowing potentials from the single output of the trigger 8 and the zero output of the trigger 4 (FIG. 1) trigger the single-vibrator 16 of the second information rewriting unit 5 (FIG. 2). The pulse from its output passes through the element OR 19 and records the overhead word in the register transmitter 3 (pulse 58, 6), then the pulse is delayed by element 15 for the duration of the pulse, passes through the element OR 17 and resets the trigger 8 to zero the After that, the pulse is delayed by the element 14 for the time of the transition process when the gc unit 5 is rewritten to rewrite the information. Suspension of the trigger 8, sets d through the element OR 19, pulses 64 trigger 4 to one (pulse 59) and, passing through the element OR I 8, resets the buffer register 7 to zero.

(Fig. 7) are fed to the control input of the register-transmitter 3 and shifted. to the right of the case, which is located in it, the service word recorded by program in register-receiver 1 is rewritten in register-transmitter 3.

Zero status of trigger 2 allows further data writing to receiver register 1. The first word of the transmitted data array written to receiver register 1 is similar to the buffer register 7, while trigger 8 is reset.

The second word of the transmitted danlx array written to the receiver register

1 remains in it, and the trigger 2 is set to one.

Simultaneous location of triggers

2.4 and 8 in one state and pa

i.e. the resolving potential from the output of the element AND 47 (Fig. 5) passes through the element OR 50 and cocks the trigger 52 into one state. The resolving potentials from the flip-flops 51 and 52 are fed to the inputs of the AND 49 element, from whose output the sig-nap BUT is fed to the control input of the external device (WU) 6 (the beginning of the output signal of the BUT in Fig. 6 is indicated by the dotted line).

In response to the BUT signal, the external device issues a series of ICs, the number of which is equal to the number of bits of the register-receiver 1. The first IC goes to the single input of the trigger 51 of the block 11 and sets it to the single state. The inhibitory potential from the zero output of the flip-flop 51 stops the signal BUT to the slave.

The IC 63 (Fig. 7) passing to the first input of the control unit 12 is delayed by the element 40 for the duration of the IC being applied to the second input.

Q element AND 33, at the first input of which the resolving potential from the output of element 37 is located, passes through elements 33 and RSHI 45 and goes to the third launch input of the second

0

five

block 5 rewriting information. Pass through element OR 19, pulses 64

(Fig. 7) are fed to the control input of the register-transmitter 3 and shifted. to the right is the service 51397925

same word. Service word from the serial output of the register-transmitter 3 in a serial format

(impulse 62, fig, 7) this impulse goes to the input, having passed through ele10

15

25

WU 6 (in this example 1000 ... 1),

Maintenance pulses are fed to the counting input of the counter 39 of the control unit 12. The overflow pulse 61 (FIGS. 6 and 7) from the output of the counter 39, whose multiplicity is equal to the size of registers 1, 3 and 7, goes to the second input of the And 35 element, to the first input of which the resolving potential from the input of the 37 arrives. Impulse 65 (Fig. 7) from the output of the element 35, the passage through the element of the IPD 29 and being delayed by the element A2 for the duration of the pulse, the safety input of the register-transmitter 3 arrives and resets it. Further, the overflow pulse is delayed by element 43 for the duration of this pulse, arrives at the zero input of trigger A and resets it to the zero state.

The inhibitory potential from the unit output of the trigger 4 is fed to the first inputs of the And 34 and 37 elements, the inhibiting potentials from the outputs of which are fed to the inputs of the OR element 28 and. creates an appropriate potential at the control input of the register-transmitter 3, putting it into recording mode.

With the installation of the trigger 4 in the zero state, the resolving potentials arrive at the inputs of the one-shot 16. and start it. The pulse from the output of the single-vibrator 16, passed through the element Q OR 19, arrives at the first input of the register 3 and records information from the buffer register 7 into it. This same pulse, delayed by element 15, passes through the element OR 17 and resets the trigger 8. Next, the pulse delayed by the element 14 enters the single input of the trigger 4 and sets it in a single state, and, passing through the OR element 18, resets the buffer register 7 (figure 2).

Setting the trigger 8 to the zero state creates a condition for starting the one-shot 25 (FIG. 3).

the delay cops 23 and OR 20, resets the trigger 2 to the zero state, and, having passed through the delay element 22, sets the trigger 8 to the one state, and, after passing through the OR element 21, resets the receiver register

So, after issuing the service word in the VU 6 to the released register-transmitter 3, the first word of the transmitted array is overwritten from the buffer register 7, and the second word of the transmitted array located in the receiver-register 1 is copied to the buffer register 7 (Fig. one

Trigger 2, being in zero state, characterizes the readiness of receiver-register 1 to receive the next word of the transmitted data array.

The service word recorded in WU 6 is analyzed, after which WU 6 gives you a Ready signal (D) 60 (Fig. 6) indicating that it is ready for an array of data.

Bus G of the control unit 12 is connected to the first inputs of the And 31 and 32 elements and through the And 38 element to the third input of And 34 and the second input of And 36. In the recording mode, all the listed And elements are blocked by the inhibitory potential from the output of the dist. - par 10, which determines the reading mode, therefore the inhibitory potential from the output of the element And 31 adjusts the register-receiver 1 to write information from the parallel input, and the register-transmitter 3 adjusts to shift with the allowing (recording forbidding) potential from the single output of the trigger from 4 that comes on the first input element AND 37, at the second input of which the resolving potential is already located, and, passing through the element OR 28, goes to the control input of the register-transmitter 3. The further transfer of the data array in the recording mode is similar to the transfer of the service word. The number of ICs entering the inputs of the counter 39 and the delay element 40 should be

thirty

35

50

The pulse output from the one-shot 25, equal to the number of bits transmitted

delayed by the element 24 for a time, ensuring the end of the transition process in the buffer register 7 at

dropping it, arrives at its entry entry and records information from the register-receiver 1. After that, this impulse, passed through ele0

five

five

0

Q

the delay buttons 23 and OR 20, resets the trigger 2 to the zero state, and, having passed through the delay element 22, sets the trigger 8 to the one state, and, after passing the OR element 21, resets the receiver-register 1.

So, after issuing the service word in the control unit 6 into the released register-transmitter 3, the first word of the transmitted array is overwritten from the buffer register 7, and the second word of the transmitted array that is located in the receiver-register 1 is rewritten into the buffer register 7 (Fig. 1) .

The trigger 2, being in the zero state, characterizes the readiness of the register-receiver 1 to receive the next word of the transmitted data array.

The service word recorded in WU 6 is analyzed, after which Woo 6 receives the Ready signal (H) 60 (Fig. 6), indicating that it is ready to receive a data array.

Bus G of the control unit 12 is connected to the first inputs of the And 31 and 32 elements and through the And 38 element to the third input of And 34 and the second input of And 36. In the recording mode, all the listed elements of And are blocked by the inhibitory potential from the output of the discharge of the registrar 10, determining the reading mode, therefore the inhibitory potential from the output of the element And 31 adjusts the register-receiver 1 to record information from the parallel input, and the register-transmitter 3 adjusts for shifting by allowing (recording the inhibitory) potential from the single output trigger 4 that comes a first input of AND gate 37, the second input of which is already permitting potential and extending through an OR gate 28 is supplied to the control input of the register-transmitter 3. A further array data transfer is performed in the recording mode is identical transmission service word. The number of ICs entering the inputs of the counter 39 and the delay element 40 should be

0

five

0

 equal to the number of bits transmitted

array of data.

After the transfer of the data array, the Ready signal is removed.

In order to implement the read mode, a unit is written to the corresponding register bit 10, and before this signal the device is reset, 5 is reset to the initial state. The resolving potential from the output of the register 10, defining the reading mode, is fed to the inputs of the AND 30-32 elements, to the other inputs of which the inhibiting potential is fed from the bus G, and to the second input of the AND 34 element, to the third input which receives the potential potential from the output of the element 38, and the first input is connected to a single output of the trigger 4, which determines the setting of the register-transmitter 3 to the recording mode. The absence of the resolving potential at the input of the element And 31 creates at the output of this element a potential that adjusts the register-receiver 1 to the mode of recording information in a parallel format. Next, the overhead word is recorded, which is written into the register-receiver-25 nick 1 and, similarly to the write mode, is rewritten into the register-transmitter 3 (Fig. 8).

A necessary and sufficient condition for the generation of the NFR signal in the reference mode is the presence of a unit in the corresponding register bit 10 and the location of the trigger 4 in the unit state.

The resolving potential from the output of the element AND 48 of the block 11 (Fig. 5) passes the element OR 50 and sets the trigger 52 to the one state. The further operation of block 11 in generating the BUT signal and the transfer of the service word from the register-transmitter 3 to the VU 6 takes place similarly to the recording mode (Fig. 8).

After receiving the service word, WU 6 generates the Ready signal 60 (Fig. 8), the resolving potential arrives at the first input of the element 31, at the second input of which there is the resolving potential determining the reading mode. From the output of the element 31, the resolving potential adjusts the register-receiver 1 to the shift mode, From the output of the VU 6, information 67 (FIG. 9) in a sequential format is fed to the serial input of the register-receiver

35

45

50

They are temporarily set to the level of the signal at the sequential input of the register-receiver corresponding to a certain number of information, and are fed to the three-input element I 30, the rest of which have the potential resolving. From the output of the element, And 3 passes through the element of the CMM 26 and is directed to the control input of the register of the receiver 1, producing an information shift. In this case, with the last bit to the word, the counter 39 overflows, the pulse 61 overflows through the element 32, the decisive potentials arrive at the other inputs, the element OR is delayed by the element 41 at the time of the transient and the register-register 1 and sets the first ger 2 to a single state. The discharging potentials at the inputs of the one-shooter 25 of the information rewriting unit 9 start it. The impulse from the output of the vibrator 25, the pass element 24 of the holder, records the information word from the register-receiver into the buffer register 7. The same time, this information is copied into the register-transmitter 3. Witness the entries in the register-transmitter 3 of the formation word of the transmitted data array There is a single trigger state 4, which reads out the register of the transmitter. When this register is read, the read pulse arrives on the bus TH of the input groups 13 of the control unit 12, passes through the OR element 29, is delayed by the element 42 and resets registers the transmitter 3 to zero, is delayed by the element 43 and resets to the trigger 4 (pulse 66, Fig. 8).

Similarly, read the entire array of transmitted data, the start and end address of which is specified in the service word

Claims (5)

Formula invented 1. A device for interfacing with an external device, containing a hyster-receiver, a register-transmitter control unit, a buffer register 1. IC, the number of which is equal to the number of register control signals, three the number of bits of the transmitted data array, is fed to the input element 46 zadder; RCs, 12-control block, shutter The output levels of the signal at the serial input of the register-receiver 1, corresponding to a certain bit of information, are transmitted to the third input of the And 30 element, for the remaining inputs of which there is a resolution potential. From the output of the element I 30, the ICs pass through the element CMM 26 and arrive at the control input of the register-receiver 1, producing information shift. In this case, the counter 39 overflows with the last bit of each word, the overflow pulse 61 passes through element 32, the remaining inputs of which receive permitting potentials, element OR 27, are delayed by element 41 for the duration of the transient process n in receiver register 1 and sets the first trigger 2 in a single state. Allowing potentials at the inputs of the one-vibrator 25 of the information rewriting unit 9 start it. The impulse from the output of the single-vibrator 25, pass delay element 24, records the information word from the register-receiver 1 into the buffer register 7. In a similar way, this information is copied to the register-transmitter 3. By the evidence of the record in the register-transmitter 3 of the information word of the transmitted data array is a single state of flip-flop 4, which permits reading of register-transmitter 3. When reading this register, a read pulse arrives on the bus TH of a group of inputs 13 of control unit 12, passes through the OR 29 element, It is supported by element 42 and resets register-transmitter 3 to zero, delayed by element 43 and resets trigger 4 (zero pulse 66, Fig. 8). In a similar way, the entire array of transmitted data is read, the start and end address of which is indicated in the control word. Invention Formula 1. A device for interfacing a computer with an external device, comprising a register-receiver, a register-transmitter, a control unit, a buffer register. control signal register, three trigger, where the group of information inputs of the receiver register forms a group of device inputs for connecting to the first group of information outputs of a computer, the group of information inputs of the control register forms a group of device inputs for connecting to the second group of information outputs of a computer, the group of information outputs of the register transmitter forms a group of outputs of the device for connecting to the first group of information inputs of a computer; single-function outputs of the first, second, third triggers form a group The outputs of the device for connecting to the second group of information inputs of a computer, the information input of the register-receiver and the information output of the register-transmitter are the input and output of the device for connection to ln |, op-1a (the 5th output of the information input of the external device, respectively); the for- mat outputs of the register-receiver is connected to the group of information inputs of the buffer register, group 25 by the second permitting input of the for30 block 35 of information outputs of which are connected to an information input information group of a register-transmitter, characterized in that, in order to reduce equipment, a readiness formation block is entered into it, two information rewriting blocks, and the first group of inputs of the logical condition of the control block forms a group of device inputs for connecting to a group of computer control outputs, the first input of logic control condition 6jroKa is connected to the clock input of the readiness building unit and is the device input for the key switch the gating output of the external device, the second input of the logic condition of the control unit is the input of the device for connecting the output device of the external device, the output of the forming unit of the control unit is the output of the device for connection to the ready input of the external device, the group of information outputs of the control register is connected to a group of enabling inputs of the readiness block and with the second group of inputs of the logic condition of the control block, the first group of outputs, the yen the horn receiver, the setup input of which is connected to the first setup output of the first rewriting unit 45 50 which connect with a group of control inputs of the world readiness and with the first launch input of the second information rewriting unit, the second startup input of which is connected to the zero output of the third trigger, the single output of which is connected to the third enabling input of the readiness shaping unit and to the third input of the logic condition of the control unit whose third output is connected to the zero input the third trigger, the unit input of which is connected to the third installation; the output of the second information rewriting unit; the fourth installation output of which is connected to zero input of the second flip-flop, a single input coupled to a third input of the first adjusting unit of information transferred Zopisi fourth adjusting the output of which is connected to the zero input of the first flip-flop, the fourth control unit output is connected to the third input of the second start rewriting information. 2. The device according to claim 1, of which is that the control unit contains a counter, ten AND elements, five OR elements, five delay elements, the counter input of which is connected to the inputs of the first, second delay elements and is the first input of the logical condition of the block; the first input of the first element I is connected to the first inputs of the second. Information, the second installation output of which is connected to the input of the record of the buffer register, the installation input which is connected to the first installation output of the second information rewriting unit, the second installation output of which is connected to the synchronous input register-transmitter, the group of control inputs of which is connected to the second group of outputs of the control unit, the first output of which is connected to the installation inputs of the first and second information rewriting units and the block the formation of readiness, the second output of the control unit is connected to the single input of the first trigger, the single output of which is connected to the first permitting input of the forming unit availability and with the first launch input of the first information rewriting unit, the second startup input of which is connected to the zero output of the second trigger, whose single output is connected to 0 five d 45 50 world readiness and with the first launch input of the second information rewriting unit, the second startup input of which is connected to the zero output of the third trigger, the single output of which is connected to the third enabling input of the readiness shaping unit and to the third input of the logic condition of the control unit whose third output is connected to the zero input the third trigger, the unit input of which is connected to the third installation; the output of the second information rewriting unit; the fourth installation output of which is connected to zero input of the second flip-flop, a single input coupled to a third input of the first adjusting unit of information transferred Zopisi fourth adjusting the output of which is connected to the zero input of the first flip-flop, the fourth control unit output is connected to the third input of the second start rewriting information. 2. The device according to claim 1, of which is that the control unit contains a counter, ten AND elements, five OR elements, five delay elements, the counter input of which is connected to the inputs of the first, second delay elements and is the first input of the logical condition of the block; the first input of the first element I is connected to the first inputs of the second. 111 the third element And, with the first and second inputs of the fourth element And and is the second input of the logical condition of the block, the first input of the fifth element And is connected to the first input of the sixth element And is the third input of the logical condition of the block, the second input of the first element And which are connected to the second inputs of the second third, sixth elements AND and the first inputs of the seventh, eighth elements AND, as well as the second input of the fifth element AND, form the second group of inputs of the logical condition of the control unit, the first input of the first element OR, ne The first input of the second element OR, connected to the first input of the third CLI element, the installation input of the counter connected to the second input of the first SHI element and the first output of the block, form the first group of inputs of the logical condition of the block, the outputs of the second elements AND and SHSh form the first group of outputs of the block , the output of the fourth element OR the output of the third delay element connected to the input of the fourth delay element, form the second group Well, the outputs of the block, the outputs of the fifth, even-for-readiness formation, the outputs of the delayed delay elements and the output of the fifth OR elements are respectively the second, third and fourth outputs of the block, while in the control unit the input of the third delay element is connected to the output of the first OR element, the third input of which is connected to the output of the eighth element And, the second input of which is connected to the output of the fourth element And, to the second input of the seventh element And and to the third input of the sixth element And, the output of which is connected to the first input the third OR element, the second input of which is connected to the output of the fifth AND element, with the first inputs of the ninth and ten AND elements, the outputs of which are connected respectively to the fourth input of the first OR element and the first input of the fifth OR element, is connected to the third input the eighth element And, with the second input of the ninth element And, with the third input of the third element And, the output of which is connected to the second inlet 40 45 50 The first and second inputs of the 11G1I element, whose output is connected to the single input of the second trigger, the single output of which is connected to the first input of the first element And, the second input of which is connected to the zero output of the first three. 4. The device according to claim 1, that is, so that the first block of information rewriting contains a single vibrator, three delay elements, two OR elements, and the first input of the first OR element is connected to the first input The second OR element is the installation input of the block, the first, second one-shot start inputs are respectively the first, second block start inputs, the output of the second OR element is the first installation output of the block, the output of the first delay element is connected to the input of the second delay element and wto eye adjusting outlet the house of the third OR element, the output of the block, the output of the third element of the Zadrotor is connected to the input of the fifth delay element, the second input of the second OR element is connected to the output of the first 12 And the third input of which is connected to the output of the second delay element, the output of the first delay element is connected to the second input of the tenth AND element and to the third input of the seventh AND element, the output of which is connected to the second input of the fifth OR element. 3. Device POP.1, characterized in that the readiness block contains two triggers, three AND elements, OR element, the output of the first AND element is the output of the block, the single input of the first trigger is the clock input of the block, the zero input of the first the trigger is connected to the zero input of the second trigger and is the installation input of the block, the first inputs of the second and third elements And form the group of permitting inputs of the block, the second and third inputs of the second element I are the first and second permitting inputs and block the fourth input of the second AND gate, soedi- nenny with a second input of the third AND gate, is a third unit permitting entrance case at block five 0 five 0 The first and second inputs of the 11G1I element, whose output is connected to the single input of the second trigger, the single output of which is connected to the first input of the first element And, the second input of which is connected to the zero output of the first three. 4. The device according to claim 1, that is, so that the first block of information rewriting contains a single vibrator, three delay elements, two OR elements, and the first input of the first OR element is connected to the first input The second OR element is the installation input of the block, the first, second one-shot start inputs are respectively the first, second block start inputs, the output of the second OR element is the first installation output of the block, the output of the first delay element is connected to the input of the second delay element and wto eye adjusting outlet block, the output of the third delay element is connected to the second input of the second OR element and is the third installation output of the block, the output of the first . 31397925 the OR element is the fourth setup output of the block; the one-shot output is connected to the input of the first delay element, the output of the second delay element is connected to the input of the third delay element and to the second input of the first OR element. 5. The device according to claim 1, about tl and h a-10 th GC e e with the fact that the second block of information rewriting contains a single vibrator, three OR elements, two delay elements, the first input of the first OR element connected to the first the input of the second element OR. and is the installation input of the block, the first, the second chipset 3anvcKa one-shot 14 and the first input of the third element OR are the first, second and third inputs of the block start respectively, the outputs of the second, third and first OR elements are the first, second and fourth block installation outputs, the output of the first delay element is connected to the second input of the second OR element and is the third installation output of the block, while the output of the one-shot is connected to the second input of the third OR element and to the input of the second delay element whose output is connected to the input of the first delay element and with the second input of the first element OR. Omiz FIG. 2 From 2 Smd (Pus.J 9u. HLC OTU 7 M 50 SC1 “§ § 53 -JT P fpus. 3 50 52 d FIG. five Yy J S l, tlf .3 Tnch Figz