SU809183A1 - Device for microprogram control with monitoring - Google Patents

Description

(54) DEVICE FOR MICROPROGRAM CONTROL

WITH CONTROL

one

The invention relates to computing and can be used in the construction of self-controlled control devices of computers and other systems.

A firmware control device is known that contains two storage units, registers, AND and OR gates, delay elements, decoders and a clock generator 1.

The disadvantage of this device is low reliability of operation, due to the lack of monitoring of its performance.

The closest to the proposed technical support and the achieved result is a device for firmware control, containing a pulse generator and a decoder of logic conditions, the output of which is connected to the information input of the register of logic conditions, the output connected to the control inputs of the elements And the first group, the installation inputs which are the inputs of the buffer register, the output of the buffer register is connected to the first inputs of the elements AND of the second group, the outputs of which

connected to the first inputs of the address register, the setup input of which is the input of the operation code of the device, and the output connected to the information input of the first decoder, the output of which is connected to

the control input of the first memory block, the first information input of the buffer register connected to the second input, the second information output - with the first input of the logical condition decoder and the first counting input

the microinstructor counter, the third information output — with the second input of the logical conditions decimator and the information input of the address counter, the fourth information input — with the second input of the address register, the microcommand counter outputs through the first And element and connected to the first input of the second And element and through the first And element connected to the first input of the second element And through the first element NOT - with the first input of the third ele

And, the output of the first delay element is connected to the second input of the second element And through the second delay element - to the first input of the fourth And element, the output connected to the second inputs

elements 4 of the second group, the output of the second element I is connected to the setup inputs of the register of logical conditions, the buffer register, the first decoder and the address counter, the output connected to the first information input of the second decoder, the output of which is connected to the control input of the second storage unit whose information input is It is the information input of the device.

The drawback of the device is low reliability due to the lack of control over the correctness of the execution of a given firmware.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved in that the device contains a third delay element, a trigger, an OR element, a fifth, sixth, seventh, eighth and ninth AND elements, a second third and fourth NOT elements, an identifier counter and an identifier decoder, the first and second information inputs of which connected to the second and third information outputs of the first storage block, respectively, and the output to the information input of the identifier counter, which has its zero input connected to the control output of the second storage block through the second element NOT to the first input of the sixth element I, and the outputs through the seventh element I to the second input of the sixth, to the first input of the eighth AND element and to the input of the third element NOT whose output is connected to the first input of the ninth element AND, the output of the first element AND is connected to the second inputs of the fourth and ninth elements AND and through the fourth element NOT to the second input of the eighth element AND, the outputs of the sixth, eighth and ninth elements AND are connected to the corresponding inputs of the element OR, the output connected to the input the rigger inverse output of which is connected to the third input of the second, the third input of the fourth and the first input of the fifth And elements, the second input of the fifth And element is connected to the output of the pulse generator, and the output to the input of the first delay element and the second input of the third And element, the output of the connected with the second information input of the second decoder and through the third delay element - with the second counting input of the microinstruction counter.

FIG. 1 shows a diagram of the device; in fig. 2 and 3 are examples of firmware execution with a distorted starting address and the number of microinstructions.

The device contains .display 1 logical conditions, the register 2 logical conditions, the first and second groups 3 and 4 elements And the buffer register 5, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth elements And 6- 14, the address register 15, the first and second decoders 16 and 17, the first and second storage units 18 and 19, the decoder 20 identifiers, the counter 21 identifiers, the counter 22 microinstructions, the counter 23 addresses, the first, second, third and fourth elements NOT 24- 27, the element OR 28, the first, second and third elements 29-31 delay, trigger 3 2, the pulse generator 33, the input 34 of the logic conditions, the input 35 of the operation code, the first, second, third and fourth information outputs 36-39 of the first storage unit, the information input 40 and the control output 41 of the second storage unit.

FIG. 2 and 3 indicate the address at which the i-th microcommand a (i 1,23) is read, to the right of the address indicate the value of the identifier (O or 1) for the given microcommand, the address of the first microcommand A, the number of microcommands Nj, the number of linear sections or single identifier values in the sequence nj (j 1,2) and parameters similar to a distorted linear sequence.

The device operates as follows. In the initial state, all the memory elements are at zero. The operation code is fed to the input 35 of the register 15 and sets the address S of the corresponding cell in the storage unit 18.

Claims (3)

The first generator pulse 30 through from. Indoor element 10, delay element 29 and element 7 sets register 5 and register 2 to zero, and the first information word from storage unit 18 is read out through first decider 16. From output 36 of memory block 18, the indirect address of the first microcommand of the next sequence is written to register 5. At output 37, counters 22 record the number of micro-instructions in the first linear sequence of the firmware. From the output 38, the counter 23 records the address of the first microcommand of this sequence, simultaneously the signals from the output 37 and 38 are fed to the inputs of the decoder 1, which forms the sign of the logical conditions to be checked and writes it to the register 2, these signals also go to the input of the decoder 20, which generates a code for the number of identifiers in the executed sequence and writes the code to the counter 21. If the sequence consists of one linear section, one is written to the counter 21. Otherwise, the counter 21 0 records the number of 19 linear sections sequentially recorded in the storage unit, of which the sequence to be composed consists. The signal from the output 39 of the storage unit 18 sets the register 15 to zero. The second pulse of the generator 33 through the element 10 and the element 8 opens the decoder 17, and the reading of the microinstructions begins from the storage unit 19. When reading each microcommand from block 19, the contents of counters 22 and address 23, respectively, decrease and increase by one. When reading the last microcommand of the first linear section, the contents of the counter 21 are reduced by one and the reading of the micro commands from the storage unit 19 continues. When reading the last microcommand of the last linear part of the sequence of single identifier signals, the counter 21 is zeroed and a single signal appears at the output of the And 12 element. Simultaneously with the reset of the counter 21, the counter 22 is zeroed out and a single signal also appears at the output of the element 16. If the sequence of micro-instructions read from the storage unit consists of one linear section, then the counters 21 and 22 will be reset when the first single value of the identifier appears. With proper operation of the device, resetting the counters 21 and 22 occurs simultaneously. Elements 13 and 14 are closed with zero signals from the outputs of elements 27 and 26, respectively, and element 11 is a zero signal from the output of element 25, which inverts a unit identifier. Therefore, at the output of the element OR 28, a signal is absent and the trigger 32 remains in the zero state. The next pulse through the open element 9 is fed to the elements 4 of group 4, and the address of the next information word is recorded in register 15 of register 5. This address is formed in register 5 depending on the code recorded in register 2 and the values of the logical conditions received at the input 34 of group 3 of the elements I. And the next clock pulse is set to N. via the open element 7 of register 2 and register 5 and starting the decoder 16. From the storage unit 18, information from the next linear sequence is read and the device continues to work as described. The operation of the device when a failure occurs in it. If the address of the first microcommand of the next linear sequence, which may occur due to a failure in the storage unit 8 at the output 38, the counter 23 or the decryptor 17, is corrupted, the firmware will switch to an unforeseen linear sequence of microcommands. Since the memory block 19 will read the sequence with another initial address, the number and time of occurrence of the unit identifier values at output 41 will not match the number of microcommands recorded in counter 22. In this case, the counters 22 and 21 will be reset. do not follow). that i; pn leads to the appearance of a single signal. 1n ii; i the output of one of the E.xmeite And 13 m.p. -4 and the subsequent triggering of the trigger. 32 Suppose that a sequence of microinstructions with parameters must be read from memory 1. Q. Nf 10, P ( 2. Let, as a result of a failure, the address of the first microcommand distorts and A, QS-. Then, after reading from the storage unit 19 microcommands with the address U13, the counter 21 will be reset, and in the counter 22 there will be a code equal to one. This will lead to the fact that at the inputs of the AND 13 element there are single signals coming from the output of the element 12 and the element 27 at the input. As a result, a failure signal will be sent through the element OR 28, which will establish the trigger 32 in the single state. The trigger 32 zero signal from its zero output will close the elements And 9, 10 and 7, and the generator 33 will stop the supply of clock pulses. After that, the device enters the mode of re-running the firmware or localizing the failure. The device works in the same way in another case, when the address of the first microcommand Ai Qie AI. Then, after reading the microcommand with the QIC address, counter 21 is reset, and a counter equal to four will be recorded in counter 22. Operation of the device in case of distortion of information on the number of micro-commands that may occur due to a failure in the memory block 18 at the output 37, the counter 22, the counter 23, the decipher 17 or the memory flare 19 at the output 41. Failures of these nodes will lead to the execution of a shortened or extended microprogram, and this, in turn, to non-simultaneous resetting of the counters 22 and 23. Suppose that instead of the microprogram with the parameters .t 0., N1 13, n 3, there is a microprogram with the parameters AI Q. ", N 1.4, n 3. Such a distortion may occur due to the fact that as a result of a failure in the storage unit 18, the NI 14 Nt code was recorded in the counter 22, one pulse was missed in the counter 22 (the code recorded in the counter was not reduced after reading microcommands, as a result of the failure of counter 23 or decoder 17 or the output of memory unit 19, one microcommand was missed. The occurrence of any of these reasons will lead to the fact that after reading the microcommand with address f3, counter 21 will be reset, and the counter 22 will be written code, pa an element. As a result, element 13 will form a failure fault that triggers trigger 32. When the firmware is executed, the number of microcommands is less than the required (Nz 4 Na), after reading the microcommand with the address, the counter 22 will be reset to zero before the arrival of the microcommand with a single value identifier and zero counter 21. At the same time, from the output of the element 6 and the element 26 the element 26 enters the inputs of the element 14 single signals, which will trigger the trigger 32. In case of failures leading to other actions tim m parameters performed by the firmware, reset the counters 21 and 22 occurs asynchronously also that the control circuit is fixed. During the operation of the firmware control unit, the operation of the decoder 20 or the counter 21 is possible, which leads to its premature zeroing or maintaining a stable non-zero state. If during the operation a premature reset of the counter 21 occurred, then a single signal appears at the output of the element 12 and arrives at the input of the element 11, another input of which receives a single signal from the element 25. At the output of the element 11 it generates a control signal which arrives at the first input of the element OR 28 and further to the single input of the trigger 32. The element 11 also generates a failure signal also in a situation when the counters 21 and 22 have simultaneously zeroed at the zero value of the identifier. This situation arises with multiple failures in two or more nodes of the device. Thus, in the proposed firmware, the control unit monitors the correct functioning of the main nodes and the correspondence of the firmware being executed. In addition, the controls in the device are self-verifiable and allow you to block the operation of the device and fix the connection of the memory elements at the time of the failure detection. This makes it possible to significantly increase the reliability of the firmware control device. Claims A device for firmware control with monitoring, containing a pulse generator and a decoder of logic conditions, the output of which is connected to the information input of the register of logic conditions, the output connected to the control inputs of the AND elements of the first group, the installation inputs of which are the inputs of the logic conditions of the device, and the outputs connected to the first inputs of the buffer register, the output of the buffer register is connected to the first inputs of the elements of the second group, the outputs of which are connected to the first The inputs of the address register, the setup input of which is the input of the device’s one’s code, and the output are connected to the information input of the first decoder, the output of which is connected to the control input of the first memory block, the first information output connected to the second input of the buffer register, the second information output with the first input of the decoder logical conditions And, the first counting input of the counter of micro-instructions, the third information output with the second input of the decoder logical conditions and information m input address counter, the fourth information output - with the second input of the address register, the outputs of the micro1 (command through the first element And connected to the first input of the second element And through the first element NOT to the first input of the third element And, the output of the first delay element connected to the second input element And through the second delay element to the first input of the fourth element And, the output connected to the second inputs of the elements And the second group, the output of the second element And connected to the installation inputs of the register their conditions, the buffer register, the first decoder and the address counter, the output connected to the first information input of the second decoder, the output of which is connected to the control input of the second storage unit, whose information input is an information input of the device, characterized in that devices, it contains the third delay element, the trigger, the OR element, the fifth, sixth, seventh, eighth and ninth elements AND, the second, third and fourth elements are NOT, the identifier counter the identifier identifier, the first and second information inputs of which are connected respectively to the second and third information outputs of the first storage unit, and the output - to the information input of the identifier counter, the tangential input of which is connected to the control output of the second storage unit and through the second element NOT to the first input the sixth element And, and the outputs through the seventh element And to the second input of the sixth, to the first input of the eighth element And to the input of the third element NOT, the output of which is connected to ne The first input of the ninth element is AND, the output of the first element is AND is connected to the second inputs of the fourth and ninth elements AND, and through the fourth element is NOT to the second input of the eighth element AND, the outputs of the sixth, eighth and ninth elements AND are connected to the corresponding inputs of the element OR output connected to the trigger input, the inverse output of which is connected to the third input of the second, the third input of the fourth and the first input of the five And elements, the second input of the fifth And element is connected to the output of the pulse generator, and the output to the input of the first delay element and the second input of the third element I, the output connected to the second information input of the second decoder and through the third delay element to the second counting input of the microinstruction counter. And - ° h n, - w 4 , 2 A, a, Sources of information taken into account in the examination 1. USSR author's certificate No. 437072, cl. G About F 9/12. 1575 2 USSR author's certificate According to the application number 2472560, cl. G 06 F 9/16, 04.04.77 (prototype).  13 Hz-s n, i , . f, j