SU1345340A1 - Checked counting element - Google Patents

Abstract

The invention can be used in automatic control and management systems. The purpose of the invention is to increase the reliability of the control. The counting element contains a counter 1, a block 2 for extracting the first pulse, a delay element 3, a NOT element 4 and 5, an AND 6-8 element, an OR 9 element and a trigger 10, an AND 17 element and an OR 18 element are entered into the device. random failure of counter 1 to have a pulse signal (one or two) on the output bus 19. When the counter I goes out, the error signal on the output bus 19 appears periodically. silt 4 joint ventures from 4

Description

The invention relates to automation and computing and can be used in systems of automatic monitoring and control.

The purpose of the invention is to increase the reliability of the control, which is achieved by introducing new design features.

The drawing shows a diagram of the counting element with control,

The circuit contains a counter 1, a block 2 for extracting the first pulse, a delay element 3, elements NOT 4 and 5, elements AND 6-8, element OR 9, a trigger 10, a setup input 11 for counter 1, a clock input 12 and a setting input 13 for the block 2 the first pulse, the input 14 of the installation in the unit and the input 15 of the installation in zero of the trigger 10, - the input bus 16, the element And 17, the element OR 18, the output bus 19,

In the drawing, the input bus 16 is connected to the clock input of the counter 1 and to the input 12 of the unit 2, the output of which is connected to the input of the delay element 3, the output of which is connected to the installation input 13 of the unit 2 and the first inputs of the elements 6 and 7, the second inputs of which are connected correspondingly with the input and output of the element 4, whose input is connected to the transfer output of the counter 1, the installation input 11 of which is connected to the output 14 of the installation in the unit of the trigger 10, the input 15 of the installation at zero of which is connected to the output of the element OR 18, the first input of which n with the output of the element And 6, and the second with the output of the element And 17, the first and second inputs of which are connected to the outputs of the elements HE 4 and 5, respectively. The output, the first and second inputs of the element OR 9 are connected respectively to the input 14 of the installation in the unit of the trigger 10, the output of the element And 7 and the output of the element And 8, the first and second inputs with the output of the element HE 5, the input of which is connected to the output of the element 3 delay , the output bus 19 is connected to the direct output of the trigger 10,

Unit 2 of the selection of the first pulse may, for example, contain a trigger and an element And, the first and second inputs of which are connected respectively to the input 12 of block 2 and to the trigger output, the inputs of the installation in zero and in the unit of which are connected respectively

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with the output of the element And and with the input 13 of the block 2p whose output is connected to the output of the element And,

The device works as follows

In the initial state, the signal at the transfer output of counter 1 is zero. The block 2 for selecting the first pulse is open and at the output of the delay element 3 the signal is also zero. These signals through the elements HE 4, 5 open the element AND 17, a single signal from the output of which through the element OR 18 enters the input 15 of the installation in the O of the trigger 10, setting and maintaining it in the initial state.

The first pulse of the input sequence supplied via bus 16 also enters the input of element 3; delays. In this case, the extraction unit 2 of the first pulse is locked and the subsequent pulses from the device bus 16 do not pass to the input of the delay element 3. After a time equal to the delay time of the delay element 3 and, accordingly, the delay time of the transfer signal in the counter 1, the output of the delay element 3 is a pulse that arrives at the first inputs of the AND 6 and 7 elements, at the input 13 of block 2, transfer, the last the initial (open) state and through the element NOT 5 to the corresponding input of the element 8. If the counter 1 is corrected and works without failures, then the pulse from its transfer output, acting simultaneously with the output pulse of the delay element 3, opens the element 6 and via item OR 13 is confirmed It gives zero state latch 10, corresponding to the absence of errors in the counter 1 (in this case the elements 7 and 8 are locked and zero signals with outputs NOT elements 4 and 5, respectively).

As a result, a failure or failure in the counter 1 pulse at its transfer output does not coincide with the output pulse of the delay element 3. There are two possible cases. The first, when the pulse at the output of the delay element 3 appears earlier than the pulse at the transfer output of counter 1, the inverted signal from the output of the transfer of counter 1 and the pulse from the output of the delay element 3 opens AND 7 and a single signal through the OR element 9 enters input 14

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trigger 10. The trigger switches to a single state and at its output an error signal appears indicating an error in the counting element. Elements 6 and 7 are locked with a zero signal from the transfer output of counter 1,

In the second case, the pulse at the output of the counter I transfer appears before the output pulse of the delay element 3, the inverted signal from the output 3 of the delay and the pulse from the transfer output of the counter 1 open the AND 8 elements and a single signal through the OR 9 element enters input 14 of the trigger 10, The trigger switches to the 1. State and an error signal appears at its output, indicating an error in counter 1, And 6, 7 and 17 elements are locked with a zero signal from the output of delay element 3 and from the output of HE 4, respectively,

In both cases, the pulse from the output of the element OR 9 also enters the input 11 of the counter 1 and sets it to its initial state. In this case, the single signals from the outputs of the HE elements 4 and 5 open the element AND 17, a single signal from which through the element OR 18 sets the trigger 10 to the initial zero state by preparing it for the next cycle of operation. With the arrival of the next pulse of the input sequence, the next cycle of the device starts. . If counter 1 failed, then the counter 1 is set to the initial state by a signal from the output of the element OR 9 and trigger 10 by the signal from the output of the element 17 through the element OR 18 is also reset to the initial state

Thus, in the event of a random failure of counter 1, an output pulse appears on the output bus 19 (one or

Compiled by A, Ranov Editor M, Nedoluzhenko Tehred.Didyk Proofreader A.Obruchar

Order 4931/54 Circulation 900 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5

Production and printing company, Uzhgorod, st. Design, 4.

45340 °

two) errors, and when counter 1 comes out of line on the output bus 19, the error signal appears periodically.

Claims (1)

Invention Formula A counting element with a control that contains a counter, a selection unit 10 of the first Pulse, a delay element, two NOT elements, three AND elements, the first OR element, a trigger and an input bus that is connected to the clock input of the counter and the clock input 15 block of the first pulse selection, the output of which is connected to the input of the delay element, the output of which is connected to the installation input of the first pulse extraction unit and to the first 20 inputs of the first and second elements AND, the second inputs of which are connected respectively to the input and output of the first element NOT whose input is connected to the transfer output of the counter, 25 the installation input of which is connected to the installation input into the trigger unit, and the output and the second inputs of the first OR element are connected respectively to the installation input into the trigger unit, with the output of the second AND element and with the output of the third element And, the first and second inputs are costly connected respectively to the transfer output of the counter and the output of the second element NOT, the input of which is connected to the output of the delay element, characterized in that, in order to increase the reliability of the control, a fourth element is introduced into it And, and the second element OR, the output, the first and second inputs of which are connected respectively to the input of the installation in O of the trigger, with the output of the first element AND and the output of the fourth element And, the first and second inputs of which 35 45 connected respectively to the outputs of the first and second elements are NOT,