SU752320A1 - Device for exchange of information between synchronous channels - Google Patents

Description

whose bridges are synchronization channel synchronization codes, and the output is connected to the input of the delay element, the first inputs of the counter and the decoder are connected to the information input of the synchronous channel, and the matching element with the line, the output of which is the synchronization channel synchronization output, the first input trigger is connected to the output of the decoder connected by the second input to the counter output and the first information output of the synchronous channel, and the output to the input of the majority element and the second information output with synchronous channel, entered the element And, the first input of the element And is connected to the output of the majority element, and the second input with the output of the element Zadarski and the second inputs of the counter and trigger, the outputs of the decoder and element And connected to the corresponding inputs of the element OR, the output of which is connected to the input of the element matching with the line.

The drawing shows the block diagram of the device.

The device contains in each synchronous channel 1 a decoder 2, element 3 AND, trigger 4, element 5 OR, element 7 zaderlski, majority element 7, element 8 matching with the line, made in the form of, for example, transformer galvanic isolation, counter 9, license. 10 synchronization, inputs 11 and 12 of the group of synchronization inputs, information input 13 and outputs 14 and 15,

The device works as follows.

Before the start of operation, the counter 9 in each channel 1 is in the initial state, and the trigger 4 is in the zero state. The operation of the device begins with the supply of pulse signals at the input 13. These signals arrive at the first inputs of counter 9 and decoder 2. Counter 9 changes its state at the end of each input pulse. After the counter 9 has accumulated the number of pulses, which is controlled by the decoder 2, and when the next input signal from the output of the decoder 2 arrives at input 13, the signal is equal in duration. input, sets trigger one to 4 n through element 5 OR enters through element 8 and output 1O to the majority elements 7 of the two other channels 1.

The signal from the single output of the trigger 4 is fed to one of the inputs of the major element 7 of its channel. When entering at least one of the inputs 11 and 12 of the exchange signals from the other channels, the majority element 7 is activated and the signal from its output goes to the inputs of the delay element 6 and element 3 I.

While there is no signal at the output of the delay element 6 to the second input of element 3, an enabling signal is supplied, in which there is an output signal of the majority element 7 through element 3 AND and element 5 OR duplicates the exchange signal at output Y.

The delay time of element 6 must be greater than the duration of the pulses at the input 13 of any channel. At the end of the input signal at input 13 in counter 9, a code is set, one more than that controlled by decoder 2. By output from element 6 under the top of counter 9, the code is set or confirmed, one less than that controlled by decoder 2, trigger 4 returns It is forbidden to go through the element 3 to the zero state and to the external signal exchange circuit from the output of the majority element 7.

Counter 9 in each channel continues to count the number of pulses arriving at input 13.

In the event that rassin chronization of all three channels occurs, the operation of the device proceeds as follows.

When a code is established in the counter 9 of one of the channels, controlled by the decoder 2, the trigger 4 is set to one and on the output 10 the exchange signal is transmitted to the majority elements 7 of the other channels. In these channels, the exchange signal does not make any switching, since the majority elements 7 receive a signal via only one input.

For each pulse arriving at input 13, the code in the counters 9 of channel 1 is changed by one unit until the counter of at least one of the channels is set to a state controlled by decoder 2.

The next input pulse at input 13 in this channel sets the trigger 4 into one state and, as an exchange signal, through element 5 OR at the output, the DO arrives at the inputs of the majority elements 7 of other channels. In the first

canapes (the numbering of the channels is conditional, the channels are named in the order in which, after being out of sync, they dial the code controlled by the decoder 2 in which the trigger 4 was set to

a single state earlier, the exchange signal from the output of the majority element 7 is fed to the delay element 6 and to the input of element 3 AND, from whose output through element 5 OR and element 8 is returned to the external exchange circuit. The inputs of the third channel receive two exchange signals, the major element is triggered, and the signal will input the delay element 6 and, through elements 3, 5, OR, and element 8, output 10. The output signals from the delay elements 6 in the first and third channels in the counters 9, a code is set, one more than that, which is monitored by the decoder 2, and on the second / channel its state is confirmed, the triggers 4 on the first and second channels return to the zero state. All three channels were synchronized with each other, for which it is sufficient to send the number of pulses equal to the number of counter states to the input of the counting device from the channels. When one channel fails, the two remaining channels work synchronously. When two channels exit from the third channel, the third one continues to operate independently, since the input signals go directly to the input of counter 9, and the presence of transformer galvanic isolation element 8 eliminates the effect of faulty channels on the channel working on the exchange circuit.

Thus, the device provides an increase in the synchronization rate of the synchronous channels, which leads to a decrease in the time the device stays in a state of failure and increases the reliability of the device.

Inventory forms of the invention A device for exchanging synchronous channel information containing a group of synchronous channels, the synchronization output of each synchronous channel being connected to the corresponding synchronization input of all other synchronous channels, the information input and output of each synchronous channel are the corresponding input and outputs of the device each synchronous channel contains a counter, a decoder, a trigger, an OR element, a majority element whose inputs are synchronization channel synchronization inputs, the output is connected to the input of the delay element, the first inputs of the counter and the decoder are connected to the information input of the synchronous channel, and the matching element with the line whose output is the synchronization output of the synchronous channel, the first trigger input connected to the output of the decoder connected to the counter output and the first information output of the synchronous channel, and the output with the input of the majority element and the second information output of the synchronous channel, characterized in that, in order to increase the the synchronous channels capacity, an element AND is entered into each synchronous channel, the first input of the element AND is connected to the output of the majority element, and the second input is connected to the output of the delay element and the inputs of the counter and trigger, the outputs of the decoder and the element AND, the output of which is connected to the input of the matching element with the line.

Information sources,

taken into account in the examination

1. USSR author's certificate number 4891O1, cl. G 06 F 3 / O4, 1974.

2. USSR author's certificate in application M 2496238 / 18-24,

cl. G 06 R 15 / OO, 1977 (prototype).

Claims (1)

SUMMARY OF THE INVENTION A device for exchanging information of synchronous channels containing a group of synchronous channels, the synchronization output of each synchronous channel being connected to the synchronization input of all other synchronous channels, the information input and output of each synchronous channel are the corresponding input and output of the device, moreover, each synchronous channel contains a counter, a decoder, a trigger, an OR element, a majority element, the inputs of which are synchronization channel synchronization inputs, and the output is connected to the input of the delay element, the first inputs of the counter and decoder 'are connected to the information input of the synchronous channel, and the matching element 2o with the line, the output of which is the synchronization output of the synchronous channel, the first input of the trigger connected to the output of the decoder connected to the output of the second input counter and the first information output of the synchronous channel, and the output - with the input of the majority element and the second information output of the synchronous channel, it is enough to supply h from the channels layer pulses equal to the number of states zo counter. If one channel fails, the two remaining channels operate synchronously. Failure of two third channels continues to operate independently, as input signa- ₃₅ ly fed directly to the input of the counter 9, and the presence element 8 galvanic isolation transformer eliminates the influence of the faulty channel to channel working by exchanging circuits. 40 Thus, the device provides an increase in the synchronization speed of synchronous channels, which leads to a decrease in the residence time of the device in the 45 state of failure and to increase the reliability of the device. which, in order to increase the throughput of synchronous channels, an And element is introduced into each synchronous channel, the first input of the And element being connected to the output of the majority element, and the second input to the output of the delay element and second inputs of the counter and trigger, the outputs of the decoder And elements are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the matching element with the line.