SU1255970A1 - Discriminator of logic signals - Google Patents

Abstract

The invention relates to computing, in particular, to means of monitoring and diagnosing malfunctions of logic circuits. The purpose of the invention is to increase credibility. The device contains a buffer amplifier 3, an inverter 4, differentiating elements 5 and 6, triggers 7 and P, a delay element 12, a decoder 13 and a display unit 14. The introduction of elements AND 8 and 9 and the element OR IO eliminates false combinations of signals at the inputs of the decoder 13 when recognizing multiple transitions from 1 tin O and vice versa. 2 Il. with SL yes / g /

Description

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The invention relates to computing, in particular, to means of monitoring and diagnosing malfunctions of logic circuits.

The purpose of the invention is to increase the reliability by eliminating false combinations of signals at the inputs of the decoder when recognizing multiple transitions from O to

About in G- and vice versa.

Figure 1 shows the discriminator of logical signals; figure 2 - types of recognizable transients and the corresponding combinations of signals at the inputs of the decoder.

The device contains inputs and 2 buffer amplifier 3, inverter 4, differentiating elements 5 and 6, trigger 7, elements AND 8 and 9, element OR 10, trigger 11, delay element 12, decoder 13, display unit 14, interrupt trigger 15, input 16 controls

Input 1 of the device is connected to the input of the buffer amplifier 3. Input 2 of the device is connected to the synchronization input of the first trigger 7, to the input of the delay element 12 and the installation input to the state O of the second trigger 11. The output of the buffer amplifier 3 is connected to the information input of the first trigger 7, the input of the inverter 4, to the input of the differentiating element 6 and to the fourth input of the decoder 13. The forward output of the first trigger 7 is connected to the input of the element AND 8 and the input of the decoder 13, the inverse output of the first trigger 7 is connected to the input of the second element a AND 9. The output of inverter 4 is connected to the input of differentiating element 5 The output of differentiating element 5 is connected to the input of element AND 8. The output of differentiating element 6 is connected to the input of element AND 9. The output of element AND 8 is connected to the first input of element OR 10, To the second input of which is connected the input element AND 9.,.

The output of the element OR 10 is connected to the installation input to state 1 of the second trigger 11. The output of delay element 12 and the direct output of the second trigger 1 1 are connected respectively to the inputs of the decoder 13. The control input 16 is connected to the third input of the decoder. First output is decrypted

55970

13 is connected to the display unit 14. The second output of the decoder 13 is connected to the output 15 of the discriminator interrupt.

As the first trigger 7, the usual D-type trigger can be used, and the second trigger 1 1 - the RS-type trigger. As the decoder 13, you can use JQ to beat the decoder for four information inputs that have a synchronous input. Printing devices, various information display devices with storing measurement results, etc. can be used as display elements.

The device works as follows.

When recognizing a multiple transition from O to I, the signals on the first, second and fourth inputs of the decoder 13 must be set to O, 1, 1, respectively (Fig. 2, line 7).

In order to recognize the transient, the input 1 of the discriminator is connected to the studied point of the circuit. After that, a test is applied to the inputs of the monitored device, the cycle duration of which -. (I.e., the time interval between adjacent changes of the input: signals of the circuit under study) is selected from the condition

45

35

  R

Where

I,

L- constant element time

12 delays;

- the maximum possible duration of the transition process in the studied point of the scheme.

From the beginning of the application of the test to input 2, a short pulse is applied, the duration of which is chosen from the condition

h t.

Where

t pulse width; time from the beginning of the application of the test to the circuit inputs to the beginning of a change in the signal level at the point under study.

This impulse sets the second trigger 11 into О and contributes to recording the first trigger 7 of the signal level that occurred at the circuit point under study before its first

changes in the next cycle, in this case, the signal value is O, and is fed to the input of delay element 12. The changes in the signal level at the controlled point are amplified - 5 with a buffer amplifier 3 and fed to the input of differentiating element 6, and through inverter 4 to the input of differentiating element 5. Elements 5, 6 and inverter 4 are designed to detect the transition from O to 1 (element 6 and from 1 to O (element 5 and inverter 4 j. In the case of a signal transition from level O to level 1, a pulse of positive polarity appears at the output of differentiating element 6-15. If the signal changes from 1 to O, then a pulse appears at the output of element 5.

Since in the initial state (at the beginning of the test at 20) the signal at the controlled point was O, the trigger 7 will be set to the O state and a signal equal to 1 will be set at its inverse output, which will prepare element 9 for the Era-25 the zero signal at the direct output of the trigger 7 closes the element AND 8. The output from the differentiation of the first element 6 passes through the open element AND 9, the element OR 10 at the installation input into state 1 of the second trigger 11, the transfer to the last. single state. Thus, after the end of the transient processes to the controlled-5 point of the circuit, the following values are established at the first, second and fourth inputs of the decoder 13: at the first input connected to the output r of the first trigger 7, - O, at the second, connected to the output of the second trigger 11-, on the fourth, connected to the output of the buffer amplifier 3, - 1. With the arrival of the signal from the output of the delay element 12 (the signal delayed by time T) to the synchronization input of the decoder 13, his inputs. The signal from the decoder 13 is fed to the input of the block 14 jg display.

If it is necessary to recognize a certain type of transient in the circuit under study and output a signal of the residual from the device output 15, the decoder 13 is configured using the control input 16.

Claims (1)

Invention Formula The discriminator of logical signals, buffer amplifier, inverter, two differentiating elements, delay element, two triggers, decoder, display unit, the input of which is connected to the first output of the decoder, the first input of which is connected to the direct output of the first trigger, the second input - with direct the output of the second trigger, and the third input - with the control input, the information input of the discriminator is connected to the input of the buffer amplifier, the output of which is connected to the input of the first differentiating element, and through the inverter with i the house of the second differentiating element, the second output of the decoder is connected to the output of the discriminator's chipset, which is different in that in order to increase reliability by eliminating false combinations of signals at the inputs of the decoder when recognizing signals containing multiple transitions from, O to, two elements are entered into it And, the OR element and the synchronization input connected to the sync input of the first trigger, to the input of the second trigger of the second trigger and through the delay element with the decoder's pink input, the fourth input of which is connected to the buffer amplifier, the outputs of the first and second differentiating elements are connected respectively to the first inputs of the first and second elements AND, the second inputs of which are connected respectively with the inverse and direct outputs of the first trigger, the information input of which is connected to the output of the buffer amplifier, the outputs of the element. in and connected to the inputs of the element OR, the output of which is connected to the installation input of the second trigger, the second trigger is made RS - trigger. Editor N. Dankulich Compiled by N.Pom Ksheva Tehred I. Popovich Proofreader M. Pojo Order 4820/46 Circulation 728 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG. 2