SU1527636A1 - Device for checking digital units - Google Patents

Abstract

The invention can be used in computing and can be used in the development of devices with built-in control. The purpose of the invention is to increase the reliability of control of digital blocks by checking the checked blocks on several code rings. The monitoring process begins with the arrival of a signal on the start bus 15, as a result of which the contents of the zero cell of the first memory block 3 goes to the second group of inputs of the shift register 2, which, together with the modulo 1 block 1, is a signature analyzer that minimizes the output information of the monitored block 4. Comparison unit 7 compares the final signature in shift register 2 with the reference signature contained in the second memory block 6. In case of a mismatch of the signatures at the output of the noncomparison of the comparator unit 7, a signal appears that is output to the output 10 of the device malfunction signal. If the signatures contained in the second memory block 6 and in the shift register 2 coincide, then the signal from the comparison output of the comparison block 7 goes to the summing input of the address counter 5, initiating a new cycle of operation. If all control signatures coincide with the corresponding reference signatures of memory block 6, then an overflow pulse from the output of the address counter 5 arrives at the device health output 19. By forming and analyzing several signatures on several code rings, the reliability of the control is significantly increased. 2 Il.

Description

ha with a reference signature contained in the second memory block 6. In case of a mismatch of the signatures at the output of the noncomparison of the comparator unit 7, a signal appears that is output to the output 10 of the device malfunction signal. If the signatures contained in the second memory block 6 and in the shift register 2 coincide, then the signal from the comparison output of the comparison block 7 is fed to the summation

entry of the counter 5 address, initiating a new cycle of work. If all control signatures coincide with the corresponding floor signatures of memory block 6, then an overflow pulse from the code of the counter 5 of the address arrives at the output 19 of the device operability. By forming and analyzing several signatures on several code rings, the reliability of the control is significantly increased. 2 Il.

The invention relates to computing and may find application in the development of devices for controlling digital equipment.

The purpose of the invention is to increase the reliability of the control.

Figure 1 presents the scheme of the control device; 2, a time diagram of the operation of the device for the case of a properly controlled block.

The device contains a unit 1 modulo-two adders, a shift register 2, a memory block 3, a monitored block 4, a counter 5, a memory block 6, a comparison block 7, a clock pulse generator 8, And 9 element, a device fault output 10, an element OR 11, counter 12, trigger 13, element OR 14, start input 15, reset input 16, delay elements 17 and 18, service output 19.

The device works as follows.

Before starting work, the device receives a signal. input 16, which passes through the OR I4 element and sets to nt, the left state of the register

2, resets the counter 12 to the zero state, sets the monitored block 4 to the initial state and triggers the zero state 13. At the same time, the reset signal sets

to zero state counter 5. I

Start signal through the element ШИИ 11

passes to the read input of block 3; as a result, the contents of the zero block of the block are written to register 2

3. Simultaneously, the start signal passes through the element 18 and enters the installation input of the trigger 13. Element And 9 opens, and the pulses from the output of the generator 8, the passage through

0

five

0

five

0

five

0

five

element And 9, are fed to the synchronization inputs of the register 2, the controlled unit 4 and the summing input of the counter 12, initiating their work.

Binary numbers generated by an autonomous generator consisting of register 2, block 1 and controlled block 4, from a group of outputs of register 2 are fed to a group of inputs of a controlled block 4 and to a second group of inputs of block 1. Reactions of a controlled block 4 to input test influences enter the form of binary combinations to the first group of inputs of block 1, thereby participating in the formation of the next test number in register 2. Thus, register 2 with block 1 is a signature analyzer that minimizes the output information Rui-th controls unit 4,

After a certain number of pulses, the pulse from the overflow output of counter 12 is fed to the read input of block 6 and to the control input of block 7. This compares the number contained in register 2 with the reference signature contained in the zero cell of block 6. At the same time, the overflow pulse The passage through the element OR 14 causes the device to reset. If the indicated numbers do not match, at the output of the non-comparison block and 7 a signal is generated which is output at output 10.

Claims (1)

Invention Formula A device for controlling digital blocks, containing a shift register, a clock pulse generator, a modulo-two adder block, a c5 block the first counter, the trigger and the element I, and the output of the non-comparison of the comparison unit is the output of the device inequality, characterized in that, in order to check the validity of the control, the first and second elements OR the first and second elements are entered into it delays, the first and second memory blocks, the second counter, the first group of inputs of the block of the modulo two adder is informational 1 input device for connecting to the outputs of the monitored block, the outputs of the block of modulo-two adders are connected to the first group of inf The shift inputs of the shift register, the bit outputs of which are connected to the second group of inputs of the modulo-two adders block, the first group of information inputs of the comparator block and the device outputs for connection to the inputs of the digital block being monitored, are equal to the comparison block input to the counting input of the first counter and the input of the first delay element, the output of which is connected to the first input of the first OR element, the second input of which is the device start input, the output of the first OR element is connected to in House second delay element and the input of the read 2 7636 the first memory block, the outputs of which are connected to the second group of information inputs of the shift register, the bit outputs 1G of the first counter are connected to the address inputs of the first and second memory blocks, the outputs of the second memory block are connected to the second group of information X inputs of the block ) Q comparison, in (the clock pulse generator current is connected to the first input of the element And and the synchronous input of the trigger, the output of which is connected to the second input of the element And, the output of the second  The delay element j is connected to the trigger entry input, the output of the element I is the output of the device for connection to the synchronized input of the monitored digital block and connected to the syncro 20 input of the shift register and the counting input of the second counter, the output of which is connected to the second input of the second block memory, the resolution of the comparison block and the first input 25 of the second RShI element, the output of which is connected to the reset inputs of the trigger, the second counter, shift register, the second input of the second 11II element is the input of the initial setup JQ of the device and connected to the input of the NONKI first counter, the loan output of which is the output of the health of the device. tp Compiled by V.Lesienko Editor V.Petrash Tehred L.Serdyukova Proofreader V. Kaezaiy Order 7511/53 Circulation 668 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 Subscription