SU1411750A1 - Device for checking digital blocks - Google Patents

Abstract

The invention relates to computing and can be used to monitor and diagnose digital blocks using the signature analysis method, primarily for embedded control. The aim of the invention is to increase the reliability of the control by analyzing signatures at intermediate points in the input sequence. The device contains a block of 1 modulo-two adders, a shift register 2, a generator of 4 clock pulses, AND 5 and 8 elements, counters 6 and 15, a comparison block 7, a memory block II, a trigger 12, a delay element 14, and an Element OR 17. During the operation of the device, the entire input sequence is divided into parts, each of which is calculated and written into a memory block with a reference signature. In the process of control, partial signatures are formed and compared with reference values. The analysis of signatures at intermediate points in the input sequence significantly increases the reliability of the control. I il. with (L

Description

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The invention relates to computing and can be used to monitor and diagnose digital blocks and nodes, mainly for embedded control.

The purpose of the invention is to confirm the validity of the control by analyzing the signatures at intermediate points in the input sequence.

The drawing shows the functional diagram of the device.

The device contains a block I modulo two adders, a register 2 shift. Indicated monitored digital block 3c. In addition to TorOs, the device contains a generator of 4 clock pulses, the first element AND 5 ;, the first counter 6, unit 7 cpaBHeHHHj the second element And 8e output 9 of the health signal, output 10 of the malfunction signal, block 1 of the memory, trigger 12,. input 13 Start element 14 delay, the second counter 15, the input 16 reset and the element OR 17.

The device works as follows.

Before starting work, the device receives a signal at the reset input 16, which passes through the OR element 17 and sets the shift register 2 to the initial state, resets the first b and second 15 counters (clock cycles) to the initial state, sets the initial state - block 3 and to the zero state trigger 12 Next signals on input 13 Start trigger 12 is set to one. The first element And 5 opens and the pulses from the output of the generator 4, the passage through the first element And 5, arrive at the synchronization inputs of the shift register 2 monitored by block 3 and the counting input of the first counter b, initiating their operation

Binary numbers generated by an autonomous generator from the output group of the shift register 2 are sent to the first group of inputs of the comparison unit 7, to the group of inputs of the monitored unit 3 and to the first group: shu of the inputs of unit I cz mators, modulo two. The reactions to the test actions of the monitored unit 3 are received in the form of binary combinations to the second group of inputs of the unit I modulators I modulo two thus participate in the formation of the next test number in the shift register 2. So the register

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2 shifts along with block 1 modulo two adders. The reactions to the test actions of the monitored unit 3 are received in the form of binary combinations to the second group of module 1 inputs of modulators modulo two, thereby participating in the formation of the next test number in shift register 2, Thus, shift register 2 together with. by module two, sz mmatorbv. modulo two is a signature analyzer that minimizes the output information of the monitored unit 3,

After a certain number of clock cycles, a pulse from the overflow output of the first counter 6 (clock cycles) is fed to the reading input of memory block 11 and to the gate input of comparison block 7. Thereby, the number contained in shift register 2 is compared with the reference signature in the zero cell of memory block 11. If these numbers do not match, the difference between the matching block output 7 generates a signal that arrives at the output 10 of the fault signal and the third input of the element OR 17, which brings the device back to its original state. When the numbers coincide, the operation of the device is not interrupted, and the signal from the overflow output of the first counter 6, passing through the delay element 14, arrives at the counting input of the second counter 15, thereby preparing the next cell of the memory block 11 to match, because the group of information outputs of the second counter 15 (cycles) is connected to the address inputs of the memory block I1,

At the next overflow of the first counter 6, the next comparison by block 7 compares the contents of the shift register 2 and the next reference signature. Thus, the device repeatedly compares the contents of the shift register 2 with the reference signatures. The number of comparisons is determined by the capacity of the second counter 15, the signal from the overflow output of the second counter 15 allows the last comparison pulse through the second element 8 to pass from the output of the comparison block 7. Thus, at the output 9, a signal for the operability of the monitored unit 3 is formed. The same signal, which is fed to the second input of the element ШШ 17, stops the operation of the device.

Thus, in the proposed device, in the control process, not only the final state of the shift register is analyzed, but also a number of intermediate states, which increases the reliability of the control.

Claims (1)

Invention Formula A device for controlling digital blocks containing a shift register, a unit of modulo-two adders, a clock generator, a comparison unit, the first element I, the first counter and a trigger, the output register group of the shift register connected to the first group of information inputs of the comparison unit, to the first group of inputs modulo-two block and is a group of device stimulation outputs for connecting to the inputs of monitored blocks, the second group of modulo-two block inputs is a group of information inputs settings for connecting the outputs of monitored blocks, the group of outputs of the block of modulo-adders two is connected to the group of information inputs of the shift register, the output of the clock generator is connected to the synchronous input of the trigger and the first input of the first element And, the second input of which is connected to the output of the trigger and the output of the first element connected, synchronized shift register, the counting input of the first counter and is with the synchronizing output of the device to connect to the synchronized input of the monitored unit, a single input trigger is input Start mouth overflow, first overflow 0 five 0 five , 0 The counter is connected to the strobe input of the comparator, the output of the mismatch of which is the output of the device malfunction signal, characterized in that, in order to increase the reliability of control by analyzing signatures at intermediate points in the input sequence, the device contains a second counter, a memory block, a second AND element, OR element and - delay element, the input of which is combined with the reading input of the memory unit and connected to the overflow output of the first counter, the output of the delay element connected to the counting input W The first counter, the group of information outputs of which is connected to the group of address inputs of the memory block; the group of outputs of which is connected to the second group of information inputs of the comparison block, the reset input of the second counter is combined with the reset input of the trigger and connected to the output of the OR element, the first input of which is the device reset input, the matching unit of the comparison unit is connected to the first input of the second element Id whose second input is connected to the overflow output of the second counter, the output of the second element I is connected to The second input of the OR element is the output of the device health signal, the mismatch output of the comparison unit is connected to the third input of the OR element, the output of which is connected to the trigger reset inputs, the shift register and the first counter, and is the output of the device to be connected to the reset input of the monitored block