SU1297062A1 - Device for checking comparison circuits - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used in the implementation of test diagnostics tools for discrete technology type units. The purpose of the invention is to increase the reliability of the control. The essence of the invention is as follows: increasing the reliability of the control by excluding shift registers from the comparison circuit and blocking false error signals at the output of the device. This is achieved by introducing counter 2 and its connections, which allows scanning the pairs of inputs of the circuit being checked, introducing the decoder 3 and its connections, which allows selecting the checked pair of codes, introducing the group of elements And 9.1-9.2 and its connections, which ensures the formation of number codes at the inputs of the comparison circuits, the introduction of new connections for the first and second elements AND and OR, which allows control of the operation of the circuit, and the introduction of new connections for the pulse generator, which makes it possible to eliminate the formation of false Signals bki and synchronize the work of the scheme. 1 il. “(L o so O O) y

Description

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11297062

The invention relates to automation and computer technology and can be used in the implementation of test diagnostics tools for ipp units of discrete technology.

The aim of the invention is to increase the reliability of the control.

The drawing shows a functional diagram of the device for monitoring chemical comparison.

The proposed device includes an on-control comparison circuit 1, a cheater 2, a decoder 3, the first 4, the second 5 and the third 6 triggers, a generator of 7 clock pulses, an error block 8, a group of elements 9.1-9.2p, the first JO and the second 11 And elements, the first 12 and 13 second elements OR, input 14 and output 15. Block 8 contains the first, second, third and fourth elements AND 16-19, the switch 20, the equivalence element 21, the WN-NOT 22 element, the 23.1-23.P output, the outputs 24.1 Less, output 24.2 Equals, output 24.3 More - outputs of the controlled comparison circuit 1.

Consider the purpose of the elements of the device to control the comparison circuits.

Scheme 1 comparison is subject to control. It is intended for comparing p-bit binary numbers and forming according to the results of comparing one of three possible signals: - output 24.1; - output 24.2; - at the exit 24.3. With proper operation of the comparison circuit 1, one and only one single signal should be present at its outputs.

Counter 2 is used to set the numbers of the checked pairs of inputs of the comparison circuit 1. It switches to the next state on the falling edge of the clock pulse arriving at its counting input. From the information output of the counter I, the code of the number written in it is removed, and from the overflow output - the overflow pulse indicating the end of the search of all 12 pairs of inputs of the tested comparison circuit 1. The counter then returns to its original state.

The decoder 3, in accordance with the codes arriving at its input, selects the pair of inputs of the comparison circuit 1 to be tested. A single signal formed on one of

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its outputs, opens the corresponding pair of elements AND 9.1 and 9. (i + l), where i is an odd number, as a result, test signals generated by triggers 4 and 5 are applied to the tested pair of inputs of the comparison circuit 1. The triggers 4 and 5 form a sequence of test signals applied to the same inputs of the tested comparison circuit 1. Both flip-flops are triggered by the falling edge of the pulses arriving at their inputs.

The trigger 6 is designed to start-stop the device. It is switched to the unit state by the Start signal to the device input 14. The resetting of the trigger 6 to the initial state is effected by the signal generated at its input R by the element OR 13. The trigger 6 controls its output signal by starting and stopping the generator 7.

A clock generator 7 is designed to form a sequence of pulses controlling the operation of the device. The pulses at its output are formed only with a single signal at its input.

Error fixing unit 8 is designed to determine the correct operation of the comparison circuit 1 and generate an error signal. The control of the operation of the comparison circuit 1 consists in checking the conformity of the output signals of the comparison circuit I with the test signal generated by the triggers 4 and 5.

The group of elements 9.1-9.2p is intended to form the number codes at the inputs of the comparison circuit 1, on which its functioning is checked.

Element AND 10 5 controls by switching trigger 4. It only passes a clock pulse to trigger input 4 only when triggers 4 and 5 are in the initial state. Element And 1 1 is assigned to generate a signal to stop the trigger 6 at the end of the monitoring cycle, when the triggers 4 and 5 are in the one state, and 2 has generated an overflow signal.

The element OR 12 generates signals to the counting input of the trigger 4 in the process of controlling the comparison circuit 1, as well as at the end of the next control phase when forming by the counter 2

overflow signal. The OR 13 element generates a reset signal to the zero input of the trigger 6 at the end of the monitoring cycle or when an incorrect operation of the comparison circuit 1 is detected and an error signal is generated at the output 15 of the device.

The device for controlling the comparison circuits works as follows.

the elements AND 9.2 n-l and 9.2p are opened and the inputs of the comparison circuit 1 are assigned the numbers ... 01 and .. ... 0. By the (n + 1) th pulse, the correctness of the reaction of the circuit 1 on these numbers is checked, counter 2 returns to the zero state, and at its overflow output, fs, the pulse that returns the trigger

In the initial state, all elements are in the zero state. On the back

the memory is in the initial state - the front of the signal from the output of the trigger 4

 nii. The installation circuits in the initial soy-trigger 5 are set to one (not shown). On signaling state. As a result

Start received at the input of 14 mouth-device proceeds to the implementation

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The trigger 6 is set to one and triggers reHepatop 7 pulses.

The first clock pulse from the output of the generator 7 is fed to the input of block 8, as a result of which the correctness of the operation of the comparison circuit 1 with is checked. At the same time, this pulse is applied to the counting inputs of trigger 4 and counter 2. Trigger 4 is set to one, and the number 2 is written to counter 2. The output signals of counter 2 at output 23.1 show a single signal that opens And 9.1 and 9.2 . As a result, these are numbers ... 0, 0100 ... 0 ... th to the inputs of the comparison circuit I are served- ... 000 ... 010, 000 ... 01. Wherein

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the second stage of the control of the comparison circuit 1, when a single signal is given on one of the inputs of the number B, i.e. . The operation of the comparison circuit 1 is monitored for p steps, after which the 2 (n + D) -th pulse returns counter 2 to its initial state, and the overflow pulse of counter 2 sets trigger 4 to one. The device proceeds to the implementation of the third monitoring step, in which on each of the n pairs of inputs cxebcj 1 of the comparison, single signals are alternately set, i.e. sequentially formed

from the number ... 0 and ... 0, i.e. and when it is working properly, zero signals are generated at outputs 24.1 and 24.2, and a single signal at output 24.3.

The second clock pulse is used to check the correctness of the response of the monitoring circuit to the numbers A and B generated by the intended clock pulse, with the result that a single signal is generated at the output 15 of the device if an incorrect response of the comparison circuit 1 is detected. On the falling edge of this pulse into the counter 3, the number 2 is recorded, according to which the decoder 3 selects the second pair of inputs (A2, B2) of the comparison circuit 1, and at its inputs

the numbers are set.,. 0, ... 0.

By the next impulse, the correctness of the response of the control circuit 1 to the numbers A and B formed at its inputs is checked, and at its end a new pair of numbers A and B is established.

Next, the device works as described. According to the nth pulse

the elements AND 9.2 n-l and 9.2p are opened, and the inputs of the comparison circuit 1 are assigned the numbers ... 01 and ... ... 0. By the (n + 1) th pulse, the correctness of the response of the comparison circuit 1 to these numbers is checked, the counter 2 returns to the zero state, and at its overflow output fs a pulse is generated that returns a trigger

 to zero state. On the back

the numbers ... 0, 0100 ... 0 ... ... 000 ... 010, 000 ... 01. Wherein

the second stage of the control of the comparison circuit 1, when a single signal is given on one of the inputs of the number B, i.e. . The operation of the comparison circuit 1 is monitored for p steps, after which the 2 (n + D) -th pulse returns the counter 2 to the initial state, and the overflow pulse of the counter 2 sets the trigger 4 to the single state. The device proceeds to the implementation of the third monitoring step, in which on each of the n pairs of inputs cxebcj 1 of the comparison, single signals are alternately set, i.e. sequentially formed

the device works as described. At the end of this monitoring step, the overflow pulse from the output of counter 2 sets the triggers 4 and 5 to the initial state, passes through the elements AND 11, OR 13 and returns the trigger 6 to the initial state. This is where the monitoring process ends.

Claims (1)

Invention Formula A device for controlling comparison circuits containing the first, second and third triggers, clock generator, first, second AND elements, first and second OR elements, and an analysis unit, the outputs of the first and second triggers, respectively, connected to the first and second tasks of the standard analysis unit, the output of which is the output of a device failure, the outputs of the first and second elements AND are connected to the first inputs of the first and second elements OR, respectively, the outputs of the first Less, Equal and More con The controlled comparison is connected to the first, second, and third information inputs of the analysis block, respectively, so that, in order to increase the reliability of the control, a counter, a decoder and a group of elements I are entered into the device, and the start input of the device is connected to a single input the third trigger, the output of which is connected to the trigger input of the clock, the output of the clock generator is connected to the synchronization input of the analysis unit, the forward input of the first And element, and the counting input of the counter, One overflow is connected to the second input of the first element OR and the first input of the second element AND, the output of the first element OR is connected to the counting input of the first trigger, the direct output of which is connected to the first input of each odd AND element of the group, with the first inverse input of the first element And, with the second input of the second element And with the counting input of the second trigger, the direct output of which is connected to the first inputs of each even element of the AND group, with the second inverse input of the first element And, and with the third input of the second element The input And, the outputs of the counter are connected to the inputs of the decoder, the i-th output of the decoder (, n) is connected to the second input of the i-element of the AND group, the output of the analysis unit is the control output of the device and is connected to the second input of the second element OR, the output of which is connected Compiled by I. Safronov Editor T. Larfenova Tehred L. Serdyukov and Proofreader I. Muska Order 783/53 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Design, 4. 0 5 five 0 with the input of the installation of the zero of the third trigger, the analysis unit contains the first, second, third and fourth elements AND, the switch, the element of equivalence and the element SHSh-NOT, and the first information input of the block is connected to the first inverse inputs of the first and second elements AND and the first input of the third AND element, the second information input of the block is connected to the direct input of the first AND element and the control input of the comparator, the output of which is connected to the first input of the OR-NOT element, the first and second inputs of the block reference are connected respectively Essentially with the first and second, inputs of an element of equivalence, the output of which is connected to the first input of the fourth element And, the first and second inputs of the task of standards are connected: respectively to the second input of the second standard And, and to the second inverse of the third element And, the output of which is connected to the first inverse the input of the switch, the second input of the standard setting of the block is connected to the second input of the third element And, and the second inverse input of the second element And, the output of which is connected to the second information input of the switch, the output ne Vågå AND gate coupled to a second input of the fourth AND gate, whose output is connected to a second input of the NOR Hilti, third information input unit connected to the inverted input OR- NO element whose output is the output unit.