SU1599861A1 - Device for monitoring units of microprogram control - Google Patents

Abstract

The invention relates to automation and computing and can be used in debugging complexes of microprogram computing and control systems. The purpose of the invention is to expand the field of application of the device by increasing the number of types of microcommands to be tested. It is achieved by the introduction of trigger 17, trigger 18, lock 18, generator 19, decoder 22, third to fifth elements OR 27 - 29, first and second switches 30, 31. However, the device for controlling the firmware control blocks contains registers of the operating part 11, address part 12, fault addresses 13, failure triggers 14 - 16, comparison circuits 20 and 21, AND 23 and 24 elements, two OR 25 and 26 elements. The essence is to provide the ability to control microprogram control units implementing "empty" microcommands with waiting "logs cic conditions. 4 ill., 1 tab.

Description

The invention relates to automation and computer technology and can be used as part of debugging complexes of microprogram computing and control systems.

The purpose of the invention is the expansion of the scope by increasing the number of types of tested microcommands.

Figure 1 shows the functional diagram of the device; figure 2 is a block diagram of the formation of the address of the teams; in Fig. 3 - fragments of the control and monitoring algorithms implemented by the microprogram control units and · corresponding coding options for the fields of the operational part, 'address, microcode instruction code; figure 4 is a timing diagram of the operation of the device.

A device for monitoring microprogram control blocks (Fig. 1) contains a controllable microprogram control block 1, consisting of 2 microcommand memory blocks with outputs 3 addresses of the next microcommand, 4 codes of the verified logical condition, 5 microoperations, 6, 7 signal labels of the types of microcommands executed, 8 the signal of the end of the firmware, driver 9 addresses, register 10 addresses, register 11 of the operating part, register 12 of the address part, register 13 of the failure address, the first and third triggers 14-16. failure, start trigger 17, lock trigger 18, pulse generator 19, first and second comparison circuits 20, 21, decoder 22, first, second / elements 23, 24, first-fifth elements 25-29, first and second switches 30 , 31, output 32 of switch 31, outputs 33-35, respectively, of failure, error, device looping, first to third outputs 36-38 of generator 19, input 39 of logical condition signals, input 40 of operation code of microcontrol unit 1, input 41 of start, output 42 indication of device address.

I

Shaper 9 addresses of the controlled unit 1 microprogram control can be performed according to one of the traditional schemes. An embodiment of the shaper 9 addresses shown in figure 2. It consists of a logical condition multiplexer 43, an adder 44 modulo two., A switch 45. In Figs. 3, 4, the notation introduced in Fig. 1 is used.

Consider the purpose of the main elements and nodes of the device.

Register 11 is used to store codes of the operational parts of the previous microcommands; register 12 - for storing the address codes of previous microcommands; register 13 - for recording and storing the addresses of the microcommands, during the execution of which the device malfunctioned or failed.

The first failure trigger 14 serves to record the failure due to physical failures at the output of 5 microoperations of the microprogram control unit 1.

The second trigger 15 of failure is designed to fix the failure due to the erroneous entry into adjacent cells of the same operational parts of microcommands with repeated operational parts.

The third trigger 16 failure is used to record the failure due to the looping of the micro-command at any address, detected by comparing the address parts of the previous and subsequent micro-commands.

The start trigger 17 is used to turn on the generator 19 when the device starts up and stops when a failure occurs in the microprogram control unit 1 detected by the device. In addition, the signal from the inverted output trigger 17 resets the register 10 of the address of the monitored block 1 firmware control.

The lock trigger 18 allows you to mask the result of comparing the addresses of the previous and current microcommands when the monitored microprogram control unit 1 passes to executing branch microcommands with waiting logical conditions.

The generator 19 is designed to form three sequences T |, T _g , Tj clock pulses that synchronize the operation of the controlled unit 1 of the microprogram control and device. At the output 36 of the generator 19, pulses of the sequence T _{o are formed} . output 37 - pulses of the sequence T ^, output 38 - pulses of the sequence T ₅ . The time intervals between the pulses of the sequences' Τ, -Τ $ are chosen ⁵ 1599861 based on ensuring the stable operation of the elements and components of the device.

The first comparison circuit 20 is for generating a signal corresponding to the fact of having the same $ ^! output operational parts of neighboring microcommands.

The second comparison circuit 21 serves to generate a signal corresponding to the fact of the looping of the microprogram (execution of microcommands with the same address).

Element And 23 is designed to generate a failure signal to the output 33 of the device when the operational part of the microcommand is equal to zero.

Elements AND 24 and OR 26-29 are designed to generate control signals of the operation of the switch 31.

The decoder 22 at one of the outputs generates a signal of the type performed by the micro-command in accordance with the table.

to devices when the addresses of the current and subsequent microcommands are equal.

Device for monitoring the operation of the firmware control blocks ^! works as follows.

In the initial state, all the memory elements of the device are reset (the initial state setting circuits are not conventionally shown in the diagram). At the same time, at the output 8 of the monitored control unit 1 of the microprogram control, a single signal is present.

Upon receipt of the start signal 41, the trigger 17 is set to a single state and turns on the generator 19.

According to the first pulse of the sequence, the address 10 of the address koht-i of the microprogramme control unit 1 from input 40 through the former 9 records the address of the first micro-command of the microprogram. At this address from block 2 of the memory microcommands

Output Code 6, 7

Decryptor Excited Output Number 22

The type of microcommand being executed is a microcommand containing the following fields:

after the address of the next micro-command (field 3); ’Code field of the checked logical condition (field 4);

microoperation field (operating

Conventional micro-command Micro-command with repeating operating part Micro-command with waiting

part, field 5); first tags (by- field signal le 6); field signal second tags (by- le 7); field signal microoperations the end

teams (field 8).

condition 11 4 Empty micro command

The OR element 25 generates a signal when the contents of the microoperation field of the performed micro command are nonzero or when the micro command with the Waiting logical condition is executed.

The switch 30 is designed to generate an error signal when the operational parts of the previous and current microcommands are equal, or if the operational parts are inequality in microcommands with repeating operational parts.

The switch 31 is used to generate a loop signal ₄ 0 The operational part of the microcommand (field 5) is fed to the first comparison circuit 20, to the information inputs of the register 11 and to the OR element 25. The address code of the next microcommand (field 3) and the code of the verified logical condition (field 4) arrive at the shaper 9 addresses and participate in the formation of the address of the next microcommands. The address code of the current microcooQQ command from the output of register 10 of the address is sent to the comparison circuit 21 and to the information inputs of the registers 12, 13. Signals of logical conditions from the control object through the input $ 39 to $ 5 go to the shaper 9 of the controlled unit 1 of the microprogram control and participate in the formation of the executive address another microcommand.

Depending on the type of micro-command performed, the operation of the device further has its own characteristics.

Execution of the usual micro-command • (see table). At the first output of the decoder 22 there will be a single signal.

By the pulse of the sequence, the test result is fixed for the operating part of the microcommand to be equal to zero in trigger 14. In parallel, the operational parts of the current and previous microcommands are compared in the comparison circuit 20, the addresses of the current and previous microcommands in the comparison circuit 21 and the test results are recorded on the triggers 15 and 16. The operational part of the microcommand from the 20 output 5 of the controlled unit 1 of the microprogram control is supplied to the OR element 25. If it is not equal to zero, then the output element nt OR 25 a single signal appears. 25 This signal passes through the element OR 28, the element And 24 and sets the trigger 14 in a single state. If the signal at the output of the OR element 25 is absent (which occurs at 33 zero t contents of the operating part of the current microcommand), then the trigger 14 remains in the zero state. If the monitored microprogram control unit 1 is functioning correctly, then there are no signals at the output of the comparison circuits 20, 21. Otherwise, the signal from the output of the first comparison circuit 20 (if an error occurs, the operational parts of the previous and current microcommands are repeated) is fed through the switch 30 to the trigger 15 and to the OR element 26. Similarly, the signal from the output of the second comparison circuit 21 when When a jamming error occurs (the addresses of the current and previous microcommands are equal), it passes through the switch 31 to the trigger 16 and to the OR element 26. The triggers 15, 16 go into a single state and form an error and loop signal at the outputs 34, 35 ', respectively. According to the signal from the output of the OR element 26, the address of the microcommand is recorded in register 13, during which the unit 1 failed, and the trigger 17 is set to zero. The generator 19 is turned off and the device stops. The address from the register 13 is supplied to the output 42 of the display.

According to the impulse T ₅ , the operational part of the current micro-command is recorded in register 11, and the address of the current micro-command is in register 12. In addition, the pulse T ₃ checks the status of the trigger 14. If the trigger 14 is in a single state (which corresponds to the correct functioning of the device), then the signal through the element And 23 does not pass. Otherwise, a signal passes to the output 33 of the failure. This signal passes through the OR elements 26, 29 to register 13 and trigger 17. In this case, the address of the microcommand with the zero operating part is recorded in register 13 and the device stops working ..

Running a micro command with a repeating operating part.

The pulse T ₄ in the register 10 of the address of the controlled unit 1 of the firmware control is recorded the address of the micro-command. A micro command is selected from this memory unit 2 and a signal appears at the second output of the decoder 22. The micro-command is formed correctly if the address of the current micro-command is different from the address of the previous micro-command (there is no signal at the output of the comparison system 21) and the operational parts of the current and previous micro-commands are the same (a signal occurs at the output of the comparison circuit 20). Upon receipt of the pulse T _g signals at the inputs of the switches 30 and 31 are absent. Otherwise, at the outputs of the switches 30 or / and 31, signals appear that trigger the triggers 15 and / or 16 and through the OR element 26 enter the address of the microcommand, during the execution of which a failure is detected, and set the trigger through the OR element 29 17 to the zero state.

When the pulse T ₃ arrives at output 33, a device failure signal is generated (if the operating part of the microcommand is equal to zero) and the operating and address parts of the firmware being executed are recorded in registers 11, 12, respectively.

Execution of a micro command with a waiting logical condition.

Controlled unit 1 functions correctly if the addresses of the previous and current microcommands coincide. Otherwise, there is a failure of the monitored control unit 1 'microprogram control. By the pulse of the sequence T _y in the register 10 is entered the address of the microcommand with a waiting logical condition. A micro command is selected from this memory unit 2 and a signal appears on the third output of the decoder 22. Through the element OR 25 and the element OR 28, this signal is supplied to the element AND 24 and masks the contents of the operating part of the micro-command. The signal from the third output of the decoder 22 is fed to the D-input of the trigger 18 lock. According to the pulse of the sequence T ₂ triggers 14, standing. According to the pulse of the sequence T ₃ , the operational part of the current microcommand is entered into register 11, and the address of the microcommand is entered into register 12. In the process of executing a micro-command with a waiting logical condition (there is a signal at the third output of the decoder 22), the trigger 18 will be in a single state.

During its execution, the operational part will be masked and the addresses of the previous and current microcommands will be compared. If they are equal (which corresponds to the correct functioning of the microprogram control unit 1), a signal appears at the output of the comparison circuit 21, which does not pass to the output of the switch 31 (trigger 18 is in a single state). If the addresses of the previous and current microcommands are not equal (which corresponds to the occurrence of an error in the operation of unit 1), then a signal appears at the output of the switch 31 at the time of the pulse of the sequence T ₂ , under which the trigger 16 is converted to unity. personal state, the address of the micro-command is recorded in register 13, trigger 17 is set to zero and the operation of the device. The swarm stops.

go into a single co1599861 10 when this is done by comparing the addresses of the current and previous microcommands. By the pulse of the sequence T ₄ in the register 10 is entered the address of the micro-command and the trigger 14 is set to zero. According to the pulse of the sequence, a signal is transferred to the output of the switch 31, cash from the output of the comparison circuit 21. If unit 1 is functioning correctly, then the signal at the output of the comparison system 21 and the switch 31 is absent. Otherwise (if the addresses of the current and previous microcommands are equal), the signal from the output of the comparison circuit 21 through the switch 31 is fed to the S input of the trigger 16 and to the OR element 26. In this case, the trigger 16 is set to a single state and gives a loop signal to the output 36. The signal from the output of the OR element 26 goes to the synchronization input of the register 13 and through the OR element 29 to the R-input of the trigger 17. The address of the executed micro-command is entered into the register 13 and the device stops working.

Further, the device operates similarly to the algorithm described above.

At the end of operation of block 1, output 32 displays the signal “End of work”. This signal through the OR element 29 is fed to the R-input of the trigger 17. The trigger 17 is set to zero and turns off the generator 19. In addition, the signal from the inverse output of the trigger 17 resets the register 10 of the control unit 1 firmware control. At the same time, a micro command containing a single signal in field 8 is read from the memory unit 2. This signal controls the transmission of the operation code from the input '40 through the shaper 9 to the information input of the register 10 of the address of the controlled unit 1 of the firmware control.

Upon receipt of the signal input 41 signal. The start-up device turns on and quotes in the same way as the described algorithm.

Claims (1)

Formula invented Funvppe Running an empty micro command. When it is executed, the results of checking the equality of the operational parts of the current and previous microcommands, the contents of the operating part of the current microcommand are masked. Checking the correct functioning of the unit A device for monitoring microprogram control units, containing the register of the operating part, the register of the address part, · the register of the failure address, three failure triggers, two comparison circuits, the first and second ele 1 1 AND, the first and second OR elements, and the input of the device for connecting to the microoperation output of the controlled microprogram control unit is connected to the group of inputs of the first OR element, the information input of the operating unit register and the first input of the first comparison circuit, the output of the operating part register is connected to the second the input of the first comparison circuit, the input of the device for connecting to the address output of the monitored firmware control unit is connected to the first input of the second comparison circuit, information by the inputs of the register of the address part and the register of the address of failure, the output of the register of the address part is connected to the second input of the second comparison circuit, the inverse output of the first trigger is connected to the first input of the first AND element, the output of which is connected to the first input of the second ~ OR element and is the output of the · A device whose start-up input is connected to the R-inputs of the second and third pages of the operating part, the address part register and the second output of the first AND element, device outputs for connecting to the outputs of the first and second labels to The microprogram control unit to be controlled is connected. Accordingly, with the first and second inputs of the decoder, the first output of the decoder 10 is connected to the second control input of the first switch and the first output of the third OR element, the second output of the decoder is connected to the third control input unit of the first switch and the second input of the third element OR, the third output of the decoder is connected to the input of the first OR element, the information input of the lock trigger and the second equalizing input of the second switch, the fourth output the decoder is connected to the fourth control input of the first switch and the first input of the fourth OR element, the output of the first 25 comparison circuit is connected to the first information input of the first switch, the output of the first OR element of failure triggers, the direct outputs of which are the error output and loop output of the 3Q device, output the second OR element is connected to the synchronization input of the failure address register, the output of the failure address register is the output of the device failure address indication, characterized in that, in order to expand the scope by increasing the number of types of tested microcommands, the device contains a start trigger, pulse generator, first and second switches, third, fourth and fifth OR elements, a lock trigger, a decoder, and the start input of the device is connected to the S-input of the start trigger whose direct output is connected to the input of the pulse generator, the first output of which is connected to the R-input of the first failure trigger and the output of the device for connecting to the synchronization input of the controlled microprogram unit control, the second output of the pulse generator is connected to the synchronization input of the blocking trigger, with the first control inputs of the first and second switches, the first input of the second AND element, the third output of the pulse generator is connected to the synchronization inputs, it is connected to the second input of the fourth OR element and the second information the input of the first switch, the output of which is connected to the S-input of the second flip-flop trigger and the second input of the second OR element, the output of the third OR element is connected to the third control input of the first switch, the $ stroke of the fourth OR element is connected to the second input of the second And element, the output of the second And element is connected to the S-input of the first failure trigger, the output of the lock trigger is connected to the fourth control input of the second switch, the output of the second comparison circuit is connected to the information input of the second a switch whose output is connected to the S-input of the third failure trigger and the third input of the second OR element, the output of the second OR element is connected to the first input of the fifth OR element, the input of the device for connecting to during operation of the microoperation signal. The end of operation of the controlled microprogram control unit is connected to the second input of the fifth OR element, the output of which is connected by the R trigger input of the trigger, the inverse trigger output of the trigger is connected to the output of the device for connecting to the installation input of the controlled micro program control block. FIG. 2 a 1 X A ^A i TO Yi  - Xj * l l 1 1 X A o ^A i r Yi l Aj'i 6 <*> DOT H Hem X A ^A i Vi Yi Xi Ajtf 2 <b> aft f Hem U 'X A ^Α ί Yi - ^A l · ⁹ - Xi ^A j * i Before | · ^And fg Yi • V .- ^A j * 3 a 1 ^A i 4 Yi ^A i "> 1 ^A j »1 Yi Yi - ^A i * z t Φί / Ζ3 ι «