SU1317442A1 - Device for checking execution of test program - Google Patents

Abstract

The invention relates to computing and allows implementation. control of the execution of a test system program on the basis of a computer with indication of the results of control, automatic start of the system on the basis of a computer at initial start-up and its restart at failure. This is achieved by introducing into the known device a generator of 3 tests, a block 4 of comparison, indicators 5,6 of malfunction, a generator of 7 clock pulses, elements AND 14,15. Using the invention frees the operator who maintains and controls the computer-based system and increases the reliability of the system in continuous work. 3 il. ff (L with vl 4 4 HS (pue.i

Description

The invention relates to computing and can be used in computer-based automated systems.

The aim of the invention is to expand the functionality of the device by monitoring the execution of the test program of the computer-based system and automatically starting the system when it is initially turned on or in the event of a crash.

Fig. 1 shows a block diagram of a device dp of monitoring the execution of a test program of a computer-based system; figure 2 - structural diagram of the generator testov; Fig. 3 is a block diagram of a comparison block.

The device contains the first 1 and second 2 clock generators, the generator of 3 tests, unit 4 comparison, indicator 5 of the number of the faulty system unit, indicator 6 of malfunction, driver 7 clock pulses, the first 8 and second 9 triggers, first to sixth elements 10-15 , element 16, device start input 17, inputs 18 and 19 of the signs of failure and passing the test, a group of information inputs 20 of the device, a group of information outputs 21 of the device, outputs of the device 7.7. - 21 for connection to the power on input, the clock input, the initial setup input, the start input and the test start input of the monitored system.

The test generator contains a memory block 28, an address counter 29, trigger 30, first 31 and second 32 elements AND,

Comparison unit 4 contains an AND element 33, And element block 34, a modulo two element block 35.

The device works as follows.

After the system has been turned on all together, the elements of the device are in a random state. When a supply voltage appears, the generators 1 and 2 are started, which begin to produce rectangular pulses with a specified period. The pulses from the output of the generator 2 arrive at the first input of the forcing device of 7 clock pulses, as a result of which clock pulses appear on its outputs sequentially in time. Let after the initial inclusion of the first trig

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The ger 8 has been set to the zero state, then the pulses from the first, second, third and fourth outputs of the sync generator 7 pass through the third, fourth, fifth and sixth elements 12-15 (the second inputs have a zero potential coming from the output of the trigger eight). Then, the pulse from the fifth output of the driver of the 7 sync pulses goes to the computer as a signal of the demand, or to launch the system tests. Since the computer is in an idle state, the response to this signal in the computer

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missing. Then, from the sixth output of the time pulse distributor, a signal is sent to the setup input of the trigger 8, under the influence of which the trigger is turned into a single state. This condition is detected by a fault indicator 6. Next, the cycle of generation by the shaper 7 clock pulses is repeated. The pulses are again sent to the first, and the inputs of the elements 12-15, and since the trigger 8 continues to be in a single state, these signals go to the outputs 23-26 of the device and then to the inputs of the computer as the power on signals of the system and the computer, starting computer clock generator, setting the starting address of computer work programs, starting computer work programs. After that, from the fifth output of the generator of 7 sync pulses with a delay C determined by the pulse following period from the output of the clock generator 2, a pulse appears that simultaneously arrives at the setup input of the second trigger 9 and at the output 27 of the device as a signal to start the tests system. If the computer and the system as a whole start up in time, the computer reacts to this signal and outputs the resolution as a system test start signal to the device input 17, which through the first element 10 arrives at the starting input of the test command generator.

In the test generator 3, the system test start signal enters the installation input of the third trigger 30 and translates it into a single state, thereby opening the valve (the seventh element H 31), which starts to pass pulses from the generator 1 to the counting input of the counter 29.

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addresses. The address counter 29, starting with zero, generates an N-bit code. In accordance with the number of incoming pulses, the address codes arrive at the address input of the memory unit 28, which leads to sequential reading of N-bit information words (codes) at its outputs. The signal from the Nth bit of the Nth bit word enters the corresponding i-th test block of the system, where it is sequentially written into its register of the test command. A fully i-test command is generated in k cycles of sequential transmission of information words from the storage device. The size of the information word depends on the number of system blocks to be tested, and the number of words in the storage device (volume) depends on the size of the test command.

The test team contains information and service part. The service part of the test command places the unit under test into the diagnostics mode, after which the information part affects the selected points of the unit under test in order to generate a diagnostic signal (symptom) that takes two states - normal and defective.

Therefore, after the k-bit d-on the test command is formed in k cycles, the k + 1-th cycle on the outputs of the test blocks should receive a signal arriving at the corresponding digit of the decoder of the number of the faulty block, which will be compared to the iM bit The home of the N-bit information word readable on the k + 1 clock cycle from the memory block 28. k + 1 information word corresponds to every i-M digit of the diagnostic sign. Every i-ro unit under test is OK. A bitwise comparison of the k + 1 information word and the signal of the response of the monitored blocks of the system to the theta commands occurs on the k + 1 cycle, when the eighth element I, connected by its inputs to the outputs of the n-bit address counter, produces an output enable signal, which . enters the second inputs of the elements AND of the block 34; the comparison block; The block 34 of the elements And passes k + 1 information word to the first inputs

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unit 35 units of comparison modulo two, to the second inputs of which signals are received from the controlled units of the system to test commands. If the comparison did not occur, for example, in the i-th bit, then the 1st element of the comparison modulo two generates a non-comparison signal, which is fed to the i-th input of the indicator as a fault signal of the i-ro system unit. Since the ninth element And its inputs are connected to the outputs of the element block 35, compared modulo two, in the case of non-comparison an input potential is present which corresponds to a signal of at least one fault in the system.

Simultaneously with the generation of a signal, the launch of a computer system test should launch a computer test program. If the test passes the computer successfully on its output register, it generates a direct and inverted signal in the corresponding adjacent bits. The computer passes the test. These signals from the computer output register register go to inputs 18 and 19, respectively, which are the inputs of the NOT element 16 and the second element And 11, where it is decrypted in order to establish the actual presence at the inputs of the device 18 and 19 of the signal to pass the test of the computer. Such decryption is necessary, since when power is supplied to the computer (i.e., when it is initially turned on), the output registers can be set both in a single and in a zero state. It is unacceptable to interpret the fact that a computer test passes separately as a direct or only inverted signal, since such a situation can lead to a fading device, i.e. when generating a signal, turn on the power supply of the system, the trigger 8 may be in the zero position under the influence of the computer output register and thus close the elements 12-15, preventing the signals from the outputs 23-26 of the device from passing, and since the output registers of the computer spontaneously change their state cannot, then, respectively, the trigger 8 does not change its state. If signals are actually present at inputs 18 and 19, then the result of their decoding goes to the installation input of the driver 7, to the faults

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the inputs of the first and second triggers 8, 9 and sets them to the zero state. Thus, in each cycle of operation of the device, determined by the cycle of operation of the imaging unit 7, the computer will receive a start signal on which (based on a specific task solved at the moment of signal arrival and determining the system block loading of both B in general and individually) according to the course of the computational process, the system test is launched or not. But the computer program of work must necessarily include commands, according to which the computer informs the monitoring device that the test program has received a signal to start the system tests as signals (direct and inverse) that the computer passes the test. The signal about passing the test of a computer should appear until the moment when the trigger 4 is set to one.

In all cases when the system crashes (suppose, due to a brief power outage), the device interaction circuit for monitoring the performance of the system test program is such that it tends to Bring the device into the same steady state — system startup mode. This mode is determined by the fact that the trigger 8, in the absence of signals at inputs 18 and 19 of the device, transfers the signal from the generator 7 to the state 1 and thereby permits the passage of signals from the generator 7 to the outputs 23-26 of the device in order to influence the computer and input system in operation. For flexible operation of the device, the generator 2 must be able to set up an external pulse frequency, which must be determined primarily by the time of the computer test.

Claims (1)

Invention Formula A device for monitoring the execution of a test program, comprising first and second triggers, first to fourth elements AND, an element NOT characterized in that, in order to extend the functionality of the device by providing an automatic start of the system upon initial power up and 7442 five 0 five 0 five 0 five 0 five restart in case of failure, a test generator, a comparison block, a failed block number indicator, a fault indicator, a clock generator, the first and second clock generators, fifth and sixth elements AND, the output of the first clock generator are connected to the device. , the group of outputs of which is connected to the first group of information inputs of the comparison unit and is a group of information outputs of the device for connection to the group, the inputs of the monitored sy topics, the second group of information inputs of the comparison unit is a group of information inputs of the device for connecting to the output group of the monitored system, the group of information outputs of the comparison unit is connected to the input group of the indicator of the number of the faulty block, the output of the decoder is the output of the generalized error of the device, the generator start input tests connected to the output of the first element And, the first input of which is connected to the start input of the device, the second input of the first element And is connected to the direct output of the first the first trigger, the input of the sign that the device does not pass the test through the element is NOT connected to the first input of the second element I, the second input of which is the entrance to the sign that the device passes the test, the output of the second element I is connected to the installation inputs of the first and second triggers the sync pulse generator input, the first output of which is connected to the installation input to 1 of the first flip-flop and is the output of the device for connecting to the input a demand for triggering tests of the monitored system, the second forming output sy pulse is connected to the input of the installation of 1 second trigger, the third output of the clock generator is connected to the first input of the third element AND, the output of which is the output of the device for connection to the power on input of the controlled system, the fourth output of the generator of clock pulses is connected to the first input of the fourth element AND whose output is the output of the device for connected to the clock input of the monitored system, the fifth output of the clock generator is connected to the first input of the fifth AND element, the output of which is the output of the device for connecting to the input of the initial installation of the monitored system. The sixth exit shaper 28 J / the sync pulses are connected to the first input of the sixth And element, the output of which is the output of the device for connecting to the startup input of the monitored system, the output of the second trigger is connected to the second inputs of the third to sixth And elements and to the input of the malfunction indicator. 21 tt 2. / S2 2B phage.2 Editor A.Makovska Compiled by M. Molchanov Tehred V. Kadar Order 2425/44 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader S. Shekmar