SU1029176A1 - Analog information input device - Google Patents

Abstract

1. DEVICE FOR INPUT ANA / AUGUST INFORMATION, containing a pulse generator, the output of which is connected to the first analog input (| (converter, the second input of which is the device input, information outputs of the analog-digital converter connected to the matching interface block, control output - with the first control input of the interface block, the information and control outputs of which are respectively the information and control outputs of the device, the second control The first input of the interface unit is the control input of the device, which is due to the fact that, in order to increase the reliability of the device, a monitoring and diagnostics unit is inserted into it, containing the control signal analyzers, the key, the first and the second load element, the terminals on; The load elements are connected to the corresponding key outputs, the output of the second load element is connected to the first inputs of the control signal analyzers, the second inputs of which are connected to the output of the pulse generator, to the control output the interface unit and the control input of the device, respectively, the first outputs of the first, second and third analyzers of control signals are connected to the third inputs of the second, third and first analyzers of control signals, respectively, the second outputs of the first, second and third analyzers of control signals are connected to the fourth inputs of the second, third and first, respectively. analyzers. control signals, the first outputs of which are connected to the fifth inputs of the third, first and W second analyzers, which control signals, respectively. S 2. A device according to nt, which means that each of the analyzers of control signals contains inverters, triggers, elements N0, AND, indicators, the third and fourth at D load elements, the delay element , ki and the OR element, the first, second and I third inputs of which, the first inputs -h1 of the first and second elements AND, the CD input of the delay element, the first input of the first trigger are the fifth, third first, second, fourth inputs and the second and first outputs. analyzer, respectively; the input and output of the delay element are respectively connected to the first inputs of the first element AND and the first trigger, the output of the element OR: connected to the second input of the trigger, the output of which is connected to the second inputs of the first and second elements

Description

AND, OUTPUTS, which are connected to the first inputs of the second and third triggers: respectively, the third input of the OR element is connected to the second inputs of the second and third triggers, the outputs of which, topMx are connected to the first inputs of the third and fourth load elements through series-connected first inverter, the first the indicator and through successively connected second inverter, the second indicator respectively, the second inputs of the third and fourth load elements are connected.

The invention relates to computing, in particular, to automatic input devices in a computer. A device for inputting analog information is known, which contains a 5 ADC control unit, an amplifier, a readout unit and an additional readout unit with their connections .1.

A disadvantage of this device is the asynchronous principle of operation, 10 in which information is sampled at arbitrary points in time, which limits the scope. .

Closest to the invention, tS is a device for inputting analog information, comprising an analog-to-digital converter (ADC), a computer interface and a pulse generator, starting the analog-to-digital converter. A random process signal is received at the input of the ADC, the generator starts the ADC with the specified frequency. The ADC outputs to the interface input a conversion result code accompanied by a data readiness signal. The interface generates a demand signal in the computer, the computer generates a sampling signal, which, arriving at the interface, resets the demand signal and reads out the result of the pre formation, which is received by the computer 2.

 In normal operation, the signals fiycK (R), the Requirement (T and Sampling (B must follow in a certain П-Т-В-П-Т-В-В -... Any errors from this order lead to errors and are Signs of faults requiring diagnostics and elimination. Causes of deviations may be a computer, ADC and interface. Due to irregular computer operation, it may not be able to select the result of measurement @e neither from the interface before the next ADC launch. have time to do the conversion in the time between the two starts. Sustainably delay the issuance of the T signal. A number of other faults are also possible, each of which can lead to information loss,

The device has reduced reliability, as it does not provide control over the correct functioning.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved by the fact that in a device for inputting information, containing a pulse generator, the output of which is connected to the first input of the analog-digital converter, the second input of which is the input of the device, the information outputs of the analog-digital converter are connected to the corresponding information inputs of the unit interface control output with the first control input of the interface block, information and control outputs of which are respectively information and control outputs device, the second control input of the interface unit is the control input of the device, the monitoring and diagnostics unit is inserted, containing the analyzers of the control signals, the key, the first and second load elements, the load element terminals are connected to the corresponding terminals, the second load terminal element is connected to the first inputs of the analyzers of control signals, the second inputs of which are connected to the output of the pulse generator, to the control output of the interface unit and to the control input of the device Respectively, the first outputs of the first, second and third control signal analyzers are connected to the third inputs of the second, third and first control signal analyzers, respectively, the second outputs of the first, second and third control signal taps are connected to the fourth inputs of the second, respectively, the third and first analyzers of control signals, the first outputs of which are connected to the fifth inputs of the third, first, and second analyzers of the control signals, respectively. . In addition, each of the control signal analyzers contains an inverter, triggers, AND elements, indicators, third and fourth load elements, delay elements and OR element, the first, second and third inputs of which, the first inputs of the first and second elements AND, the element input delays, the first input of the first trigger are the fifth, third, first, second, fourth inputs and the second and first outputs of the analyzer, respectively, and the output of the delay element, respectively, are connected to the first inputs of the first element And the first trig Era, the output element OR is connected to the second input of the trigger, the output of which is connected to the second inputs of the first and second elements AND, the outputs of which are connected to the first inputs of the second and third triggers, respectively, the third input of the element OR connected to the second inputs of the second and third triggers of the output connected to the first inputs of the third and fourth load elements through the successively connected first inverter, p € (the left indicator and through the second inverter connected in series, the second indicator corresponds to venno, the second inputs of the third and fourth load elements are connected. Fig., T shows the possible order of the monitored signals (Start-P, Requirement-T and Sampling-B) that are permissible during normal operation and are signs of elementary violations of the normal-mode of operation; figure 2 - structural diagram of the device; FIG. 3 is a block diagram of the control and diagnostics block; in fig. - functional diagram of the analyzer of logical signals; figure 5 - timing diagrams illustrating the operation of the analyzer; in fig. 6 shows time diagrams of the follow-up of monitored signals in the normal mode (Ba) and in some typical cases of disruptions in the normal mode of operation (6 B-E). With 3toM, neither Requirement nor Sampling occurs. Such a case, for example, is possible when the ADC power supply is turned off, the Monitoring and Diagnostics Unit issues the code 100000. In Fig. 6B, it shows the case when the Start request was not issued after the Start signal, but the Sampling signal (R-in) arrived. Such a case may occur, for example, if, as a result of the interference, the interface failed and did not issue a Demand signal, but the interference was taken as the Sampling signal. The control and diagnostics unit issues the code 010000. Figure 6G shows the failure of the mode consisting in doubling the signal. The requirement, which is possible, for example, with unstable operation of the Argues of the emergency unit. The monitoring and diagnostic unit in this case issues the code 001000. In FIG. 6 D shows the case when, after the generator produced a single signal, the Start-up of the interface block placed a potential signal Requirement, but the computer did not receive a Reel signal. Usually the trailing edge of the signal. him the front of the signal sample. Therefore, the absence of a Sample leads to a degeneration of the impulse. The monitoring and diagnostics unit in this case issues the code 101100. In FIG. 6E shows a case of a mode violation consisting in doubling the Wijork signal. This may, for example, be observed when the device is unstable in a computer that outputs a Sampling signal. The control and diagnostic unit issues a code. The device contains an analog-to-digital converter A / D converter 1, interface unit 2, calculator 3, pulse generator k, control and diagnostics unit G for communication between device blocks 6-12, first, second and third inputs of control and diagnostics 13-15, control analyzers 10 signals 16, 162, I6j, key G /, inputs and outputs (signals of the analyzer control signals 18-2, trig, hera 25-27, element OR 28, inverters 29 and 30, elements AND 31 and 32, delay element 33, the signal connections of the logical signal analyzer 3 and 35, the indicators 36 and 37, the start signals, demand, Sample (P, T, B), load elements. The device works as follows. A random process is input to ADC 1. Start input 6 ADC 1 is connected to generator A. Output 7. ADC 1, carrying the ordinate code of a random process, is connected to block 2 input. At the same time, the ADC output is connected to the second link of link 2 8. Output buses 9 of block 2 are connected to input of calculator 3. Communication between block 2 and calculator 3 serves to transmit a signal. Requirement. The connection 11 between the calculator 3 and the third input of the block 2 is designed to transmit a sampling signal. During normal operation of the device, there are three possible alternations of Start (P), Requirement (T) and Sampling (c) signals: П-Т, Т-В and В-П (figure 2. The remaining six possible variants of alternating these signals (П P, P-B, T-T, T-P, B-B and B-T can occur only when the system is not working properly and therefore are signs of elementary disturbances of the normal mode, on detecting which the device is working. Workers signals from the generator k, block 2 and number 3 Start, Requirement and Sampling are fed to the inputs 21 of the first, second, second second and third analyzers 16. At the same time, co6j 6flaeTC of the sequence of signal alternation is RTB -P-T-B-P-T-B -... This sequence includes three variants of signal interleaving: P-T, T-B and B- T, which are listed in the first column of the table (Fig. 1). The timing diagram of the analyzer signals 16 in the normal operation mode is shown in the left side of Fig. 5. Initially, when the key 17 is turned on, the triggers 25-27 in all analyzers 16 are set to zero. 6 A signal arriving at the input 21 of the analyzer 16 (Fig.) Arrives at the delay element 33 and, after a delay time that must be longer than its duration, appears at the first output 19 of the analyzer 16. And also sets the state to Trigger 25, at the inputs of the logic gates And 31. and 32 appears equal to the resolution of the signal. However, the signal at input 21 by this time becomes equal to zero and does not pass through the element 31. The signal from the output 22 is fed to the input 23 of the next analyzer 16, but cannot get into it to the input of the trigger 27, since in this analyzer the trigger 25 is reset and outputs a signal equal to zero. The signal 19 is fed to the input 20 of the next analyzer 16 and the input 18 of the previous analyzer 16 ,,,, passes through the elements OR 28 into the zero inputs of the flip-flops 25, but has no effect on them, since these flip-flops are in O. Thus, as a result of the arrival of a signal at input 21, this analyzer 16 is set to 1 flip-flop 25. If the next signal appears corresponding to the normal operation mode (Fig. 2 at the input of the next with respect to the considered analyzer 16, then all processes in this analyzer flow However, the signal 19, arriving at the input 18 of the analyzer 16 considered, resets the trigger 25 into O. The arrival of the third signal following the normal operation mode (Fig. 1) of the input of the third analyzer 16 leads similarly to the installation of the trigger 25 the third analyzer in 1 and to the reset. of this trigger in O in the second analyzer 16. The process repeats further. Elementary violations of the normal mode can be divided into two types, corresponding to the second and third columns of the table in FIG. The elementary violations of the first type (column 2) consist in the repetition of the same signals: П-П, Т-Т and В-В. A timing diagram explaining the operation of the analyzer 1b in the event of an elementary violation of the first type is shown in the middle part of Fig. 5. After the arrival of the first of the signals constituting an elementary violation of the headphone type, the trigger 25 is set, and the signal Vja at the input of the logical element I 31 also has a single value (Fig.). Therefore, the Btoi swarm of the same signal, arriving at input 21, passes through the element | 1 31 and sets the trigger 2b to one. At the same time, the signal at the output of the inverter 29 takes the value O, which causes the indicator 36 connected to it to fire. the signals at outputs 19 and 22 do not make any changes in the other analyzers 16. Thus, the ignition of one of the three db indicators connected to the inverters 29, indicates the occurrence of a corresponding elementary violation of the first type. In the third column of the Table of Figs), elementary violations of the second type are given, consisting in the appearance of unacceptable variants of alternating two different signals: PB, TP, and BT. A timing diagram, illustrating the operation of the analyzer 16, is shown in the right part of FIG. 5. After the appearance of the First signal, the trigger 25 in the corresponding analyzer 16 is in a single state. Due to this, the signal at the input of the element AND 32 is equal to the unit F (the elementary violation of the second type) second signal arrives at the input 21 of the analyzer 16 preceding (in the ring to which the first signal. This second signal appears at output 22 and enters input 23 analyzer 16, which already received the first signal, where the second signal passes through element 32 and sets 1 trigger 27 The signal 35 from the output of this trigger passes through the inverter 30 and turns on the indicator 37. The second signal arrives at the input 21 of the analyzer 16, except those described act It passes through delay element 33, sets in trigger 25 and appears at output 19. From this output, it enters input 20 of a subsequent analyzer 16 and input 18 of a previous analyzer 16. This causes resetting of the triggers in them 25 to the zero state, i.e., prepares the analyzers for analyzing further variants of signal alternation.A fire of one of the three indicators 37 connected to the inverters 30 signals the occurrence of a corresponding elementary violation of the second type. The control and diagnostics unit 5 is reset to the initial state by pressing the key 17. In this case, the triggers in the analyzers 16 are set to the zero position, and all the indicators go out. Under real conditions, deviations from the normal mode can accompany with the appearance of several variants of elementary, corresponding to two: right columns of the table (figure 1). Under these conditions, several indicators catch fire. Triggers 26 and 27 form a six-bit register that can be used to issue diagnostic data to calculator 3. At the same time, a set of ordinates of a random process can be considered Dobrokest-Vennom if, after its input, none of the indicators is lit or on triggers 2b and 27 The binary code 000000 has been retained. The introduction of a special design of the monitoring and diagnostics unit 5 makes it possible to increase the reliability of the device through timely detection and elimination of malfunctions.

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Claims (2)

1. INPUT DEVICE * '. ANALOGUE INFORMATION containing * a pulse generator, the output of which is connected to the first input of an analog-to-digital converter, the second input of which is the input of the device, the information outputs of the analog-to-digital converter are connected to the corresponding information inputs of the interface unit, the control output is connected to the first control input of the interface unit, information and the control outputs of which are respectively the information and control outputs of the device, the second control input of the interface unit It is the control input of the device, which is important in that, in order to increase the reliability of the device, a control and diagnostic unit is introduced into it, containing control signal analyzers, a key, the first and second load elements, and conclusions load elements are connected to the corresponding key terminals, the output of the second load element is connected to the first inputs of the control signal analyzers, the second inputs of which are connected to the output of the pulse generator, to the control output of the interface unit and to the control at the input of the device, respectively, the first outputs of the first, second and third control signal analyzers are connected to the third inputs of the second, third and first control signal analyzers, respectively, the second outputs of the first, second and third control signal analyzers are connected to the fourth inputs of the second, third and first, respectively. control signal analyzers, the first outputs of which are connected to the fifth inputs of the third, first and second analyzers, control signals, respectively. 2. The device according to claim 1, with t and l, characterized in that each of the \ analyzers of control signals contains inverters, triggers, elements> AND, indicators, the third and fourth load elements, delay element, ki and OR element, the first the second and third inputs of which, the first inputs of the first and second elements AND, the input of the delay element * the first input of the first trigger are the fifth, third ^ first, second, fourth inputs and the second and first outputs. of the analyzer, respectively * the input and output of the delay element, respectively connected to the first inputs n of the first AND element and the first trigger, the output of the OR element is connected to the second input of the trigger, the output of which is connected to the second inputs of the first and second elements 1029176 ' Th, exits! which are connected to the first inputs of the second, third triggers _; accordingly, the third input of the OR element is connected to the second inputs of the second and third triggers, the outputs of which are connected to the first inputs of the third and fourth load elements through a series-connected first inverter, a first indicator and through a series-connected second inverter, a second indicator, respectively, the second the inputs of the third and fourth load elements are connected.