JPS6342978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cable fault detection system, and more particularly to a system in which a standby line is provided for checking.

In general, connectors and cables are used for input/output between logical devices, between printed boards, between back panels, etc. within a logical device. In recent years, as the reliability of semiconductor devices has improved, failures in connectors and cables have become more prominent. Further, these failures often result in long-term downtime, and the present invention relates to a method for detecting such failures in connectors and cables.

Conventionally, connectors and cables are often guaranteed by performing parity checks as part of the bus. However, while parity checking is suitable for data buses, it is not suitable for control signals. Furthermore, since the detection point is performed at a register, it is difficult to isolate the faulty part, whether it is a connector, cable, or other logic circuit. Particularly when a multi-wire cable is used, it is desired to detect which wire is the fault, but this cannot be detected with a parity check.

Therefore, it is an object of the present invention to eliminate the above-mentioned drawbacks, and the object is to provide a multi-wire cable having switching circuits on each of the input line and output line sides, and to provide a multi-wire cable with switching circuits for at least one spare line. A signal generating section is provided in the multi-wire cable and synchronizes the above two switching circuits to switch to correspond to the core wire, and a circuit for checking the output signal via the switching circuit on the output side is provided in the multi-wire cable. The signal of the line to be checked is applied to the backup line, the signal applied to the line to be checked via the output side switching circuit is checked by the check circuit, and cable failures are detected by sequentially changing the line to be checked. This is accomplished by detecting.

The present invention will be explained in detail below using the drawings.

FIG. 1 is a conceptual diagram of the present invention. As shown in the figure, a spare line R is provided in a multi-wire cable C, and an input line
Synchronizing IN and output line OUT, input switching circuit IX applies the signal of the line to be checked to reserve line R, gives "0" and "1" signals to the check signal line, and outputs the signal from output switching circuit OX. Check the validity of the check circuit CH. The lines to be checked are sequentially switched and all signal lines are checked.
Note that CLKGEN is a clock signal generator.

FIG. 2 shows an embodiment of the present invention, and the same symbols as in FIG. 1 indicate the same things as in FIG. A is an AND circuit,
OR is an OR circuit, CN is a connector, SR1 and SR2 are shift registers that have only one 1 and all others are 0, and are circularly shifted, EOR is an exclusive OR circuit,
FF is a flip-flop, and CLKGEN is a clock signal generator. Clock signal generator CLKGEN
shall output a square wave with a duty of 50%,
Shift registers SR1 and SR2 use either the rising edge or the falling edge of the square wave as a shift trigger, and sequentially shift 1 in synchronization.

Now, considering the case where the lower register of shift register SR1 is "1", input line 1 passes through signal line _C1 ,
Similarly, all the lines other than the input line n reach the output line 1 through their corresponding signal lines. In contrast,
The input line n does not pass through the signal line Cn, but passes through the backup line R to reach the output line n. And the signal line Cn is
A signal from a clock signal generator CLKGEN is connected, and square wave "1" and "0" are transmitted. The contents of shift registers SR1 and SR2 are synchronized, and the contents of signal line Cn are applied to check circuit CH. Therefore, if normal, signal states of "1" and "0" are also given from the clock signal generator CLKGEN, the exclusive OR circuit EOR continues to output "0", and the flip-flop FF is not set. That is, the error signal ER
is not output.

However, if there is a fault in the signal line Cn, the exclusive OR circuit EOR outputs "1",
Flip-flop FF is set and error signal
ER is output. This will result in the detection of a cable fault.

Clock signal generator CLKGEN is “1”, “0”
Subsequently, when the signal becomes "1", shift registers SR1 and SR2 perform a shift operation in synchronization at the rising edge, and "1" is shifted to the second digit from the lowest position. Similarly, the multi-wire cables are sequentially checked by the sequential switching operations of the input switching circuit IX and the output switching circuit OX.

FIG. 3 shows another embodiment of the invention. The same symbols as in the previous figure indicate the same things as in the previous figure. In Fig. 3, shift registers SR1 and SR2 are operated synchronously, and the input switching circuit IX operates the shift registers SR1 and SR2 in synchronization.
Based on the contents of SR1, one of the input signal lines is connected to the reserve line R.
The connection to is the same as in FIG. In Figure 3, C ₁ other than the spare wire R in the multi-wire cable C
The feature is that no check signal is given to ~C _o .

Assume now that "1" is stored in the second digit from the lowest position in both shift registers SR1 and SR2. The input signal line 2 is connected to the backup line R. Output switching circuit OX is a shift register
Based on the contents of SR2, that is, _C2 is output from the OR circuit OR and given to the exclusive OR circuit EOR together with the reserve line R. Therefore, if there is no fault in the signal line _C2 , the input to the exclusive OR circuit EOR is the same, the flip-flop FF is not set, and the error signal ER indicates that there is no fault. The clock signal generation circuit CLKGEN generates shift register SR.
1 and SR2 are shifted by 1 bit and the next signal line is checked.

That is, only a shift register and a gate circuit are used as the input switching circuit IX and the output switching circuit OX, and an EOR is used as the comparison circuit, and the shift register is shifted one bit at a time by a clock signal. The signal line whose shift register is set to "1" is selected, the contents of that signal are passed through the backup line R, and the check is performed to check whether the contents that have passed through the actual signal line and the contents that have passed through the backup line R are selected. This is done by comparing the received contents. With the above-mentioned simple configuration, all n lines can perform duplication checks in a time-sharing manner.

As described above, according to the present invention, a fault in a multi-wire cable can be easily detected.

Incidentally, it goes without saying that the number of spare lines, check circuits, etc. is not limited to one or more, and there may be a plurality of them.

[Brief explanation of drawings]

FIG. 1 shows an overview of the present invention, FIG. 2 shows an embodiment of the invention, and FIG. 3 shows another embodiment of the invention. In the figure, C is a multi-wire cable, R is a spare line,
IN is an input line, OUT is an output line, SR1 and SR2 are shift registers, IX is an input switching circuit, OX is an output switching circuit, CH is a check circuit, CLKGEN is a clock signal generator, and ER is an error signal.

Claims (1)

[Claims] 1 A multi-wire cable that has switching circuits on each of the input line and output line sides, where the multi-wire cable is provided with at least one spare line, and a signal that synchronizes the two switching circuits and switches them to correspond to the core wire. A generating section and a circuit for checking the output signal that has passed through the output side switching circuit are provided, and the signal of the line to be checked in the multi-wire cable is applied to the reserve line, and the output signal is passed through the output side switching circuit. 1. A cable failure detection method characterized in that a signal applied to a line to be checked is checked by the check circuit, and a failure in the cable is detected by sequentially changing the line to be checked.