JPH01209502A - Checking device for extension bus of programmable controller - Google Patents

Abstract

PURPOSE:To surely detect the abnormality by transferring the check data to the extension unit of the final stage via all extension bus signal lines to adversely transfer the check data again via said signal lines and comparing the transferred data and the adversely transferred data. CONSTITUTION:A selector 32 and a reception side control circuit 42 of an extension unit 9 of the final stage are set in a check processing state respectively by a check mode signal 37 of a control signal generating circuit 36 of a basic unit 1. The extension bus check data is written into a storage device 39 and at the same time sent onto an extension bus address signal line 34. The circuit 42 stores the bus check data into a reception data storage device 40. Then the data stored in the storage device 40 is sent again onto the line 34 and stored in a reread signal storage device 48. This data is compared with the check data stored in the storage device 39 by a comparator 49. If no coincidence is obtained from said comparison, a noncoincidence output signal 50 is activated. In such a way, the short circuit or the release of an extension bus signal line can be surely detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an additional path check device in a programmable controller (hereinafter referred to as PC).

[Prior Art] Normally, in order to increase the number of input/output points in a PC,
In addition to the unit equipped with the basic part, a plurality of extension units are connected by extension cables, and data is exchanged between each extension unit and the basic part via a common bus that includes the extension cables.

FIG. 3 shows a PC system in which these basic units and a plurality of extension units are connected by extension cables. In FIG. 3, reference numeral 1 denotes a basic unit, which is a CPU section 2.1 that executes control and monitoring of the entire device, processing of the Kneesaburotarum, collection of input/output data, etc. A user program memory 3 that stores user programs, a data memory 4 that stores data necessary for user program processing, and a data memory 4 that is provided between the expansion bus and the CPU section, controls the bus interface 7510 of the expansion unit 9, and controls input/output. It is composed of a bus control section 5 that sends and receives data, and a connector 7 for connecting an extension cable 8. The expansion unit 9 includes a bus interface section l that controls data exchange between the plurality of input/output modules 11 and the bus control section 5 of the basic unit 1.
Basic side connector 12 that connects O and the extension cable 8 on the basic unit side, Extension connector 13 that connects the extension cable to the next stage, Basic side connector 12 and Extension connector 1
3 and an internal expansion unit bus pattern 14 for connecting bus signals between the bus interface section 10 and the bus interface section 10.

By the way, in a PC as shown in FIG. 3, the extension bus control unit 5 and the connection connector 5, which constitute the extension bus, are connected to each other. ,
12,13. Expansion cable 8. Path interface section 10. A short circuit or open failure of the bus signal occurs in the path pattern 14 or the like in the expansion unit. As a method for detecting abnormalities in these buses, a configuration that performs a parity check as shown in FIG. 4 is conventionally known.

In FIG. 4, when data is output from the basic unit l to the expansion unit 9, the output data is transmitted from the basic unit internal data bus 16 to the data bus driver 18 of the bus control section 5, to the basic unit internal expansion bus pattern 29, to the connecting connector. 7, the data is transmitted to the data bus receiver 25 of the bus interface unit IO via the extension cable 8, the basic side connector 12 in the extension unit, and the bus pattern 30. At this time, parity bit information created by the parity generator 17 based on this data is added to the data sent from the basic unit 1, and the data is sent to the parity checker 26 of the expansion unit 9 via the output data parity signal line 22. communicated. It is determined whether or not the parity is correct based on the received data and the added parity bit information, and from this it is determined whether or not the data has been transmitted correctly.The determination result is sent to the output data parity abnormality notification signal line 21.
The basic unit 1 is notified by this. When data is manually transferred from the expansion unit 9 to the basic unit 1, the presence or absence of an abnormality can be detected in the basic unit 1 in substantially the same manner.

[Problems to be Solved by the Invention] However, with the parity check method as described above, due to the nature of parity, it may not be possible to detect abnormalities depending on the occurrence pattern of bus short circuits and open failures. That is, if an abnormality occurs in a plurality of buses in a group of bus signal lines and the parity eventually becomes correct, there is a problem in that the parity cannot detect the error.

The present invention has been made in view of the above-mentioned problems, and
P that can reliably detect abnormalities in the expansion bus
The purpose of the present invention is to provide an additional bus check device for C.

[Means for Solving the Problems] To this end, the present invention provides a programmable controller in which a basic unit and one or more extension units are connected in series by an extension bus signal line group, the programmable controller being provided in the basic unit and connected to an extension bus. The connector to which the signal line group is connected, the first and second connectors provided in the expansion unit to which the expansion bus signal line group is connected, and the connection status of the expansion bus signal line group in the second connector. a next-stage presence signal generation means for changing the signal logic by changing the signal logic; and a storage means for storing data to be transferred via the bus signal line forming part of the expansion bus signal line group based on the data setting of the data setting means; a received data storage means for storing data on the bus signal line; and a received data storage means for transferring the data in the storage means to the bus signal line;
After that, write means for storing the data on the bus signal line in the received data storage means, read-back signal storage means for storing the data on the bus signal line, and data in the received data storage means are transferred to the bus signal line, and then, a readout means for storing the readback signal in the storage means; a comparison means for comparing the data in the storage means with the data in the readback signal storage means and outputting a predetermined signal when the comparison does not match; and a comparison means for storing the data in the storage means. A data setting means for sequentially shifting and setting data for each comparison so that one of the data groups to be transferred to a bus signal line group including a bus signal line is different from the others, and a next stage presence signal generating means are connected. The present invention is characterized in that it includes a data exchange prohibiting means for prohibiting data exchange at the extension unit provided with the connected second connector when generating a signal corresponding to the second connector.

[Operation] According to the above configuration, the data for checking the extension bus signal line is transferred to the final stage extension unit via all the extension bus signal lines connected to the extension unit, and then the data for checking the extension bus signal line is transferred to the final stage extension unit. It is reversely transferred via the signal line. The reversely transferred data and the transferred data are compared, and if they do not match, a predetermined signal is sent out.

Also, the data to be transferred is transferred to one of the expansion bus signal line groups.
The data of the two additional bus signal lines are set differently.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the expansion bus control section 5. of the basic unit 1 in the PC system shown in FIG. This figure shows in detail one branch of the bus interface section lO of the expansion unit 9 and the group of address bus signal lines connecting therebetween, and each of the other address signal lines also has a circuit as shown in FIG. It is equipped with Further, each of the other signal lines in the expansion bus, ie, the control bus and data bus signal lines, also has a bus check circuit similar to that for the address signal line, which will be described in detail below.

As mentioned above, the configuration shown in FIG. 1 can be configured as part of the PC system shown in FIG.
Therefore, the CPU 2 executes the control according to the embodiment of the invention described below in FIG.

In the bus control unit 5 shown in FIG. 1, 36 is a control signal generation circuit, which generates check mode signals 37 . Write strobe signal 41.
A read signal 44 is generated. 39 is a memory device, CP
It is connected to U2 by a data bus signal line 38. As a result, the CPU 2 writes a data signal "H" or "L" for checking the expansion bus into the memory 39 based on the data setting. 32
is a selector, which switches between normal data transfer and data transfer related to additional path check processing in response to a check mode signal 37 from a control signal generating circuit 36.

That is, the CPU side address signal 31 or the memory 3
Switch the contents of 9 and send it. 33 is an address driver, which increases the electric energy of the signal passed through the selector 32 and sends it to the additional bus address signal line 34.

Reference numeral 48 denotes a read-back signal storage device that stores received data read back from the bus interface section IO of the expansion unit 9. Reference numeral 49 denotes a comparator that compares the contents of the read-back signal storage and the contents of the storage 39, and when the comparison results in a mismatch, the mismatch output signal 50 is activated.

In the bus interface section lO of the expansion unit 9, 42 is a receiving side control circuit, and the control signal generating circuit 36
Bus interface section 1 according to various control signals from
Controls data transfer within 0. Reference numeral 40 denotes a received data storage device which stores the data on the address signal line 34 based on the received data storage pulse from the receiving side control circuit 42 during expansion pass check processing. A reception data driver 45 sends the contents of the reception data storage to the address signal line 34 based on a driver gate enable signal 46 from the reception side control circuit 42.

When the check mode signal 37 is "non-active", it means normal data transfer, so the receiving side control circuit 42 becomes stationary due to the non-active state of the check mode signal 37. As a result, the signal on the address signal line 34 The data is transferred to the internal bus 6 shown in FIG. 3 and subjected to normal processing.

Note that the check for additional buses according to the present invention is not performed using the various control signal lines output from the control signal generation circuit 36. Therefore, in order to increase the reliability of this control signal line, the signal line pattern is made thicker, and the mutual spacing is kept wide to prevent open circuits and short circuits.

The details of the connection connector 7, the basic side connector 12, and the extension connector 13 are as shown in FIG.
The two terminals of the expansion connector 13 and one terminal of the expansion connector 13 are connected to the logic signal voltage 0 [V], and the expansion connector 1
One terminal of 3 is connected to the logic signal voltage 5 [V] and the receiving side control circuit 42 via a pull-up resistor 52 and a next-stage signal line 51. With this configuration, when the extension cable 8 is connected to the extension connector 13, that is, when the extension unit 9 having the extension connector 13 is further connected to the extension unit 9, the next stage presence signal line 51 becomes "active." , the active state of the next stage presence signal is inputted to the receiving side control circuit 42. At this time, if the check mode signal 37 is "active °°", the bus interface section 10 is in a static state with respect to the signal of the extension bus. Become.

As a result, the extension cable is not connected to the extension connector 13, and therefore the next stage presence signal line 51 indicates that the "non-active" extension unit is the final stage extension unit furthest from the basic unit 1. The transmission and reception of signals for the extension bus check shown below is performed between the basic unit! and this final stage extension unit.This makes it possible to check all the extension cables 8 (extension buses) along the way. Become.

The main part of the expansion pass check process based on the above configuration will be explained with reference to the flowchart of FIG.

In step 521, the check mode signal 37 of the control signal generation circuit 36 is activated. As a result, the expansion path check process is started, and the selector 32 and the receiving side control circuit 42 of the final stage expansion unit 9 are set to the check process state. Next, in step 522, data "H" or "L" for checking the extension bus is written into the memory 39 based on the data set in advance to be shifted, and simultaneously transferred onto the extension bus address signal line 34. In step S23, the bus check signal generation circuit 36 sends out the write strobe signal 41, and in step S24, the receiving side control circuit 42 receives this and outputs the write strobe signal 41 to the received data storage 4.
Sends a received data storage pulse 43 to bus 3
4. Store the above data. Continuing, step 525
The bus check control generation circuit 36 outputs a read signal 44 as a pulse, and the reception side control circuit 42 that receives this read signal 44 sends out a driver gate enable 46 to the reception data driver 45 in step S26. The data stored on the expansion bus address signal line 34 is transferred again onto the expansion bus address signal line 34, and then the data on the expansion bus address signal line 34 is stored in the read-back signal storage 48.

Next, in step S27, the check data stored in the storage device 39 and the data stored in the readback signal storage device 48 are compared by the comparator 49, and if they do not match, step 52 is performed.
At step 8, the mismatch output signal 50 is made active, and if it is a match signal, the process ends without any change.

Above, we have described the sequence of writing, reading back, and comparing one time for one bus signal line, but at the same timing as this sequence, bus check signal transmission/reception and comparison are executed on other address bus signal lines as well. It will be done.

When writing only one of the address bus signal lines into the memory 39, this sequence is executed using a check pattern that is different from the signal logic level of the other signal lines, and the address bus signals having different signal logic levels are executed. By sequentially shifting the lines and executing the sequence, it is possible to reliably detect short circuits and open failures in the additional bus signal line.

[Effects of the Invention] As is clear from the above description, according to the present invention, data for checking the extension bus signal line is transmitted to the final stage extension unit via all the extension bus signal lines connected to the extension unit. and then reversely transferred again via all the additional bus signal lines.

The reversely transferred data and the transferred data are compared, and if they do not match, a predetermined signal is sent out.

Also, the data to be transferred is transferred to one of the expansion bus signal line groups.
The data of the two additional bus signal lines are set to be different.

As a result, it has become possible to reliably detect a short circuit or an open circuit in each bus signal line of the additional bus signal line group.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a flowchart showing the main part of the extension bus check process in the embodiment, and Fig. 3 is a PC system consisting of a basic unit and an extension unit. FIG. 4 is a block diagram showing a configuration for parity check in the extension cable shown in FIG. 3. 1... Basic unit, 2-CPU. 3... User program memory, 4... Data memory, 5... Bus control section, 6.16... Basic unit internal bus, 7... Connection connector, 8... Extension cable, 9. ...Expansion unit, lO...Bus interface section, 11...Person output module, 12...Basic side connector, 13...Extension connector, 14-Addition! Intra-unit bus pattern, 15-- input/output bus, 17-- parity generator, 18-- data bus driver, 19-- input data receiver, 20-- input data parity checker, 21-- Parity abnormality notification signal line, 22... Output data parity signal line, 24... Input data parity signal line, 25... Data bus receiver, 26... Parity checker, 27... Input data driver , 28...input data parity generator, 29...
- Expansion path pattern in the basic unit, 30... Bus pattern, 31... CPU side address signal, 32... Selector, 33... Address driver, 34... Extension bus address signal line, 35...・Additional unit internal address signal, 36... Control signal generation circuit, 37... Check mode signal, 3a... CPU side data bus signal, 39... Memory device, 40... Received data memory device, 41... Write strobe, 42... Receiving side control circuit, 43... Received data storage pulse, 44... Read signal, 45... Receive data driver, 46... Driver gate enable, 47... ... Received data storage signal line, 48... Readback signal storage, 49... Comparator, 50... Mismatch output signal, 51... Next stage presence signal, 52... Pull-up resistor.

Claims (1)

[Scope of Claims] 1) A programmable controller comprising a basic unit and one or more extension units connected in series by an extension bus signal line group, the programmable controller comprising: a basic unit and one or more extension units connected in series by an extension bus signal line group; a connector to be connected; a first connector and a second connector provided in the expansion unit to which the expansion bus signal line group is connected; a next-stage presence signal generating means for changing signal logic; and a storage means for storing data to be transferred via a bus signal line forming a part of the expansion bus signal line group based on the data setting of the data setting means. , a received data storage means for storing data on the bus signal line; and a write means for transferring the data in the storage means to the bus signal line and then storing the data on the bus signal line in the received data storage means. , read-back signal storage means for storing data on the bus signal line; read-out means for transferring data in the received data storage means to the bus signal line and then storing it in the read-back signal storage means; and the storage. Comparing means for comparing the data of the read-back signal storage means with the data of the read-back signal storage means and outputting a predetermined signal when the comparison does not match; data setting means for sequentially shifting and setting for each comparison so that one of the data groups to be transferred to the line group is different from the others; and when the next stage presence signal generation means generates a signal according to the presence of connection. 1. An extension bus check device for a programmable controller, comprising: data exchange prohibition means for prohibiting the exchange of data in an extension unit provided with the connected second connector.