JPH08149100A - Phase difference absorbing method and digital communication equipment - Google Patents

Abstract

PURPOSE: To reduce circuit scale by dividing the phase difference of writing timing and reference timing into plural prescribed phase differences and absorbing the differences by sharing them by plural memories. CONSTITUTION: The phase comparison part 21a of a phase monitoring circuit 2a compares the phases of writing timing and reference timing and divides the phase difference into the phase difference by a time slot unit and a remainder phase difference. At this stage, when the number of bit in which phase absorption amount 22a is advanced is judged, phase amount to be absorbed by a memory ESM 12 is transmitted to a reading timing generation part 23a by using a prescribed phase amount sharing expression. The phase difference information on the advancing state of the writing timing is transmitted to a host device 15. As a result, since a generation part 23a generates the reading timing corresponding to information and transmits the timing to the ESM, the data delayed by a prescribed bit is read by the writing timing. The device 15 transmits phase amount to be absorbed to the speech path control memory SCM of a time switch 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous transfer mode transmission method used, for example, in a speech path switching part in an exchange.

Generally, the memory size of the elastic store memory (ESM) in the call path switching portion is determined in consideration of the cable length connecting the transmitting side and the receiving side. When becomes extremely long, the memory size of ESM becomes very large, and the circuit scale becomes large accordingly.

Further, when the phase absorption amount of the extension line is larger than the specified value, the phase absorption amount is changed. Since this change is made in the off-line state and the memory size is expanded by using the memory memory size changeover switch or the like, a momentary interruption occurs due to the changeover of the switch.

Therefore, it is necessary to suppress the increase in the circuit scale and the interruption due to the increase in the cable length.

[0005]

2. Description of the Related Art FIG. 11 is a configuration diagram of a main part of a conventional example, and FIG.
FIG. 7 is an operation explanatory diagram of FIG. The operation of FIG. 11 will be described below with reference to FIG.

First, as shown in FIG. 11, the receiving device is an elastic store memory (hereinafter abbreviated as ESM) 12
It has a time switch 13 including a clock supply circuit 14, a speech path memory (hereinafter abbreviated as SPM), and a speech path control memory (hereinafter abbreviated as SCM).

The transmitter 11 sends data, write timing, and a transmission clock (not shown) to the receiver via the corresponding lines. The receiving device writes the input data to the ESM 12 using the transmitting side clock and the writing timing, reads the written data in parallel using the reading timing from the clock supply circuit 14 and the receiving side clock (not shown), and outputs the time switch 13 Add to SPM in.

Writing to the SPM is performed in order from the start address using a reference timing (hereinafter referred to as a reference frame), but reading from the SPM uses an SCM in which the reading order from the host device 15 is stored. Corresponding data is sequentially read and used as output data.

The frame transmitted from the time switch 13 is generated inside the time switch using a reference frame (pulse indicating the head of data), and the frame is transmitted at the head position of the output data from the time switch. .

Next, when the length of the cable connecting the transmitter and the receiver reaches, for example, about 20 m, the data sent by the transmitter is delayed by about 100 ns. If this delay is equivalent to 20 bits as shown in Fig. 2, the amount of delay is ESM.
If absorbed by, ESM requires memory size (depth) of 20 bits.

Here, the ESM memory size is the cable length.
It was decided from the beginning of the design in consideration of (at the longest time), but there are cases where the limitation on the cable length is necessary due to the limitation of the circuit scale. However, if you have to consider extremely long cables, the memory size of the ESM will be significantly larger.

On the other hand, when the amount of phase absorption required when the line is expanded exceeds the memory size of the ESM, it is necessary to expand the amount of phase absorption by a memory size changeover switch or the like. In addition, when adding a line in the online state, one line is placed in the offline state before the line is added. After the addition is completed, the line is returned to the online state.

[0013]

As described above, as the transmission path becomes longer (especially in the case of long-distance transmission by the optical cable), the ESM must absorb all the phase amounts, so that the circuit scale is large. Becomes larger, the reliability is lowered, and the power consumption is increased.

Further, when the phase absorption amount of the extension line exceeds the specified value, the phase absorption amount is changed. Therefore, the phase absorption amount is expanded by the memory capacity changeover switch or the like after the offline state. There may be a momentary interruption during expansion.

An object of the present invention is to reduce the circuit scale and to switch the memory size without interruption.

[0016]

According to a first aspect of the present invention, a phase difference obtained by comparing the phases of a write timing and a reference timing generated on the transmission side is compared with a phase difference of a time slot unit and a residue position. Divide into phase differences. Then, the first memory absorbs the phase difference of the surplus, and the second memory absorbs the phase difference of each time slot unit so as to be absorbed.

According to a second aspect of the present invention, the phase difference obtained by comparing the writing timing generated on the transmitting side and the phase of the reference timing on the receiving side is used as the phase difference of the time slot unit and the phase difference of the remainder. There is provided a first phase monitoring circuit including a phase comparison / absorption amount calculation part which is divided into two parts and sent out, and a read timing generation part.

Then, the read timing generation section generates the read timing so that the phase difference of the input remainder can be absorbed and sends it to the first memory, and the control section absorbs the phase difference of the input time slot unit. The configuration is such that read control of the second memory is performed so as to be possible.

According to a third aspect of the present invention, a phase monitor circuit holds a phase difference detected by the phase monitor circuit, a phase difference held by the phase hold circuit, and a phase difference output by the phase monitor circuit. And a phase comparison circuit that sends a fault notification to the control means and inserts null information into the frame to which the fault notification is sent when it is detected that the comparison result is outside the allowable range.

According to a fourth aspect of the present invention, a line connecting the phase holding circuit and the control means is provided. When the control means detects the failure notification, it sends a phase reset instruction to the phase holding circuit via the line. The phase holding circuit updates the held phase difference to the phase difference sent by the phase monitoring circuit.

According to a fifth aspect of the present invention, the transmitting side is provided with the second memory, the control means, the transmitting side clock supply circuit for generating and supplying the reference timing, and the phase of the reference timing and the read timing sent from the receiving side. There is provided a second phase monitoring circuit having a phase comparison / absorption amount calculation part for transmitting the phase difference in time slot units among the phase differences obtained by comparison.

Further, the receiving side is provided with a first memory to which the data read from the second memory is written and read, and a receiving side clock supply circuit for generating and supplying the read timing.

Then, the control portion controls the reading of the second memory so that the phase difference of the input time slot unit can be absorbed, and the receiving side absorbs the remaining phase difference at the read timing.

A sixth aspect of the present invention is a phase comparison obtained by comparing the phases of input write timing and read timing with the first memory having a memory size capable of accommodating a plurality of lines each consisting of three types of lines. A phase comparator circuit that discriminates whether or not the result is within the allowable phase difference range that is held, and sends a discrimination result if it is outside the allowable phase difference range, and a deviation from the allowable phase difference range when the discrimination result is applied. Timing to detect an appropriate memory size using a built-in table, generate write side switching timing and read side switching timing using write timing and read timing, and send them to the first memory. And a generation circuit.

When the write side switching timing and the read side switching timing are applied to the first memory,
The write address and the read address are expanded or reduced to switch to the determined memory size.

[0026]

In the first aspect of the present invention, when the total amount of phase to be absorbed is n bits, the phase amount (n-am) is stored in the first memory (ESM in FIG. 1) and the second memory ( SPM in FIG. 1 corresponds to) and the remaining phase amount am bits are shared (a and m are positive integers).

For example, in the case of n = 20 bits and a = 8 bits, the phase absorption amount of the first memory is 4 bits and the phase absorption amount of the second memory is 16 bits because m = 2. Second
According to the present invention, in the receiving side, the phase monitoring circuit takes in the write timing and the reference timing (same as the reference frame) generated in the transmitting side, and calculates the phase amount to be absorbed by the first memory (the above-mentioned Similarly, the read timing is set to 4 bits and the read timing is sent to the first memory.

The first memory writes the input data from the beginning using the write timing, reads the data in the first memory from the beginning using the read timing sent from the phase monitoring circuit, and switches the time. To the second memory within.

At this time, since the input frame of the time switch is generated using the reference timing, a phase shift (for example, 16 bits as described above) occurs in time slot units from the beginning of the time slot. .

The phase monitoring circuit sends the set phase difference information between the read timing and the reference timing to the control means (the upper device in FIG. 1 corresponds to the SCM). The control means performs address conversion based on the sent information so that the remaining phase amount can be absorbed by the second memory, and controls reading of the second memory.

In the third aspect of the present invention, the phase monitoring circuit takes in the write timing and the reference timing, sends the phase difference between the two to the phase holding circuit, and the phase holding circuit stores the values. Then, the value stored in the phase holding circuit and the phase difference between the write timing and the reference timing constantly monitored by the phase monitoring circuit are fetched into the phase comparison circuit and the two values are compared. If it is out of the range, the control means is notified of a failure and blank information is inserted into the data.

In the fourth aspect of the present invention, the control means instructs the phase holding circuit to reset the phase upon receipt of the fault notification from the phase comparison circuit. When the phase holding circuit receives the phase reset instruction, it takes in the phase difference between the write timing and the reference timing from the phase monitoring circuit and stores the value. As a result, no blank information is inserted in the data.

According to a fifth aspect of the present invention, the receiving side sends the read timing to the transmitting side, and the phase monitoring circuit fetches the read timing and the reference timing, and the second memory (SPM in the time switch). ) Is the amount of phase that should be absorbed (
As above, calculate (for example, 16 bits), set the input frame and send it to the time switch.

The phase monitoring circuit sends the phase difference information (that is, 16-bit delay) of the input frame set as the reference timing to the control means. Therefore, the control means performs address conversion on the basis of the sent information so that the time switch can absorb the 16-bit phase amount and controls the reading of the second memory.

In other words, conventionally, the first memory absorbs the entire phase difference between the write timing and the read timing, but as described above, in the first to fifth inventions, the phase amount to be absorbed is set. Although the first memory and the second memory share the processing, the circuit scale of the first memory also decreases as the amount of phase absorption decreases.

According to a sixth aspect of the present invention, the phase comparison circuit compares the write timing and the read timing with each other. At this time, when it is necessary to expand the memory size of the first memory, an internal table is used to determine an appropriate memory size and the information is sent to the timing generation circuit.

The timing generation circuit generates a memory size instruction signal at the read timing and sends it to the first memory. When the first memory accesses address 0,
Since the write / read address is expanded by this instruction signal, the memory size can be increased or decreased without instantaneous interruption.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the essential parts of the first and second embodiments of the present invention, FIG. 2 is an explanatory view of the operation of FIG. 1, and FIG. 3 is a essential part of another embodiment of the second present invention. FIG. 4 is a configuration diagram of a main part of the third embodiment of the present invention, and FIG. 5 is a configuration diagram of a main part of the fourth embodiment of the present invention.

FIG. 6 is a schematic view of the essential parts of the fifth embodiment of the present invention, FIG. 7 is an explanatory view of the operation of FIG. 6, and FIG. 8 is a schematic view of the essential parts of another embodiment of the fifth present invention. 9 is a configuration diagram of a main part of the sixth embodiment of the present invention, and FIG. 10 is an operation explanatory diagram of FIG.

Here, the same reference numerals denote the same objects throughout the drawings. Further, the first memory and the second memory in the claims are the ESM and SPM in FIGS. 1, 3 to 6 and 8, the control means is the host device and the SCM, and the reference timing is the reference frame. Correspond.

The phase difference between the write timing and the reference frame is assumed to be 20 bits as in the conventional example, and FIGS. 1 to 10 will be described below. In the figure, ESM is an elastic store memory, SPM is a speech path memory, and SCM is a speech path control memory. In the following description, abbreviations are used.

First, FIG. 1 shows a configuration in which a phase is absorbed at the input side of the time switch 13. Data and write timing (timing pulse indicating the beginning of data) from the transmitter 11 in the figure and a transmitter not shown When the clock is input to the receiving side, the receiving side uses the write timing to transfer the input data to the ESM.
Write to 12.

On the other hand, the phase comparison part in the phase monitoring circuit 2a
21a compares the phase of the write timing with the reference frame and sends the comparison result to the phase absorption amount calculation part 22a. The phase absorption amount calculation part 22a judges that the write timing is advanced by 20 bits from the reference frame based on the applied comparison result, and the ESM should be absorbed in the read timing generation part 23a by using the above phase amount sharing formula. The information that the phase amount is 4 bits and the phase difference information that the writing timing is 16 bits ahead of the reference frame are sent to the host device 15 (see FIG. 2).

Therefore, the read timing generation portion 23a generates the read timing corresponding to the information and sends it to the ESM 12, so that data delayed by 4 bits from the write timing is read from the ESM 12 and the time switch 13 is read. Apply to the channel memory (SPM) in the.

On the other hand, the host device 15 performs address conversion based on the sent phase difference information so that the SPM can absorb the 16-bit phase amount and sends it to the speech path control memory (SCM). By this information, SPM control that absorbs the deviation of the time slot is performed and the data is read from the time switch.

As a result, the heads of the frames of the output data sent by the time switch coincide, and the delay is eliminated. It should be noted that this frame was generated by the time switch using the applied reference frame.

FIG. 3 shows a case in which the output side of the time switch 13 is controlled to absorb the phase. The configuration is almost the same as that in FIG. 1, but the connection is slightly different. For example, the reference frame is sent only to the phase monitoring circuit 2a, and the frame to the time switch 13 is sent as a frame a signal indicating the head of the ESM output data. Further, the output of the phase absorption amount calculation portion is also sent to the clock supply circuit 14.

Now, the operation of FIG. 3 will be described, but the parts described in detail in FIG. 1 will be briefly described. Phase monitor circuit
Similarly to the above, 2a calculates the phase amount to be absorbed by the ESM as 4 bits from the input write timing and the reference frame, sets the read timing, and sends it to the ESM.

Therefore, the data written to the ESM 12 at the write timing is read at the read timing from the phase monitoring circuit (four bits behind the write timing) and written to the SPM in the time switch. Added. The frame is also added from the ESM to the time switch,
The frame and the head data temporally match each other.

Further, the phase monitor circuit 2a sends the information that the output data of the ESM is 16 bits ahead of the reference frame to the host device 15 and the clock supply circuit 14, so that the host device sends the sent information. Based on, the time switch 13 sends a read command to read with a delay of 16 bits (that is, a read address converted so that 16 bits can be absorbed) to the SCM.

Therefore, the SCM controls the reading of the SPM in accordance with this instruction, so that the output data of the time switch 13 is delayed by 16 bits with respect to the reference frame. On the other hand, the clock supply circuit sends a pulse delayed by 16 bits as a frame, so that the data whose frame coincides with the output data of the time switch is sent to the outside.

FIG. 4 shows a phase comparison circuit 4 having the same structure as that shown in FIG.
The phase monitor circuit 2a compares the input write timing with the phase of the reference frame and adds the comparison result to the phase difference comparison portion 41a. On the other hand, the phase holding circuit 3 adds the held comparison result (called a holding comparison result) to the phase comparison part 41a. The selector SEL normally selects the ESM side.

The phase difference comparing portion 41a compares the values of the holding comparison result and the comparison result, and if the comparison value is within the allowable range, it does not send the drive signal to the selector SEL, so the output data of the ESM is sent through the selector. Apply to time switch.

However, if the comparison value is out of the allowable range, the phase difference comparison part 41a sends a failure notification to the higher-level device via the null information sending part 43a and the failure information sending part 42a.
The null information sending portion sends a drive signal to switch the selector SEL to the phase comparison circuit side, inserts null information into the data of the frame judged to be faulty, and sends it to the time switch.

On the other hand, the host device sends a control signal to the SCM so that the null information inserted in the frame is not read from the SPM and sent as output data. This ensures that no noise is sent to the person talking.

In FIG. 5, a bus is provided between the host device 15 and the phase holding circuit 3. When the fault notification from the phase comparison circuit 4a is applied, the host device issues a phase reset instruction to the phase difference holding portion 31 in the phase holding circuit 3 via the bus.

Upon receipt of the phase reset instruction, the phase difference holding portion 31 fetches the phase difference between the current writing timing and the reference frame from the phase monitoring circuit 2a and updates the holding comparison result so far. As a result, the updated holding comparison result is sent from the current phase difference sending part 32 to the phase comparison circuit, so that the comparison value is within the allowable range and empty information is not inserted in the data, and the call disconnection as described above occurs. Does not occur.

FIG. 6 shows a method of absorbing the phase at the input side of the time switch when the data output from the time switch 13 of the transmission side device is stored in the ESM 12 at the reception side and read out. In FIG. 6, the data from the previous stage is applied to the SPM in the time switch.

On the other hand, the phase difference comparison portion 21b in the phase monitor circuit 2b compares the reference frame from the transmission side clock supply circuit 14b and the read timing from the reception side clock supply circuit 14a when these phases are applied. In comparison, for example,
The comparison result with a phase difference of 20 bits is sent to the absorption amount calculation part 22b.

Similarly to the above, the absorption amount calculation part 22b calculates the phase absorption amount in the time switch to be 16 bits and sends it to the input frame generation part 23b and the host device 15. The input frame generation part 23b sends a pulse delayed by 16 bits to the reference frame (pulse indicating the beginning of data) to the time switch 13 as a frame. The host device also uses the information sent to send a read command (read address converted so that the 16-bit phase amount can be absorbed) to be read 16 bits behind the time switch to the SCM in the time switch ( (See FIG. 6).

Then, the SCM follows the input read command.
The data is read from the SPM and sent as output data to the receiving side. At this time, the pulse matched with the head of the output data is also sent to the receiving side as the write timing.

On the receiving side, the data is ESed using the write clock (not shown) and the write timing sent from the transmitting side.
Write to M 12. Then, the receiving side clock supply circuit 14a
The data written in the ESM 12 is read using the read timing from (4 bits behind the input write timing), and the read data is data delayed by 4 more bits.

The frame transmitted from the ESM 12 is
It is generated by ESM using the read timing. 8 is almost the same as the configuration of FIG. 6, but the connection is slightly different. For example, the reference frame is added to the phase monitoring circuit 2c and the time switch 13, and the writing timing on the receiving side uses the one generated by the phase monitoring circuit. The reference frame coincides with the beginning of the data applied to the time switch.

Now, the phase monitor circuit 2c of the transmitting side device is arranged to receive the read timing from the clock supplying circuit 14b in the receiving side device and the reference frame from the clock supplying circuit 14a in the own device to apply the internal phase difference comparison part. 21c compares the phase difference, and the absorption amount calculation part 22c uses the comparison result to calculate the phase amount that should be absorbed by the time switch 13 (16 bits in the same manner as above), and the upper device (e.g., processor) 15 send.

The host device 15 sends a read command to the SCM in the time switch by using the sent information to read the time switch with a 16-bit delay. Therefore, the SCM reads the data from the SPM according to this read command and sends it as output data to the receiving side device.

At this time, the output frame (not shown) sent by the time switch is shifted by 16 bits from the head of the output data. Therefore, this output frame is not used, and the write timing generated in the write timing generation part in the phase monitoring circuit is sent to the receiving side device together with the output data, so that the write timing is generated.

In the receiving side device, as in the above, the remaining phase amount of 4 bits to be absorbed by the ESM is absorbed by the ESM and sent out to the outside. In FIG. 9, the memory size of the ESM 12 in the figure is 8 bits or more, but when only the transmitter 1 is used, the memory size of the ESM is set to 8 bits. Further, the thin right arrow in FIG. 10 indicates before writing / reading is executed, and the thick right arrow indicates after writing / reading is executed.

Now, the phase comparison part 41b in the phase comparison circuit of FIG. 9 compares the read timing from the clock supply device 14 and the write timing from the transmission device 1 and outputs the comparison result to the phase difference identification part 43b. Send to. Where Figure 10
In the case of (a) before expansion (transmitter 1 only), the write address was executed up to 7 bits, while the read address was 2 bits.
Since up to bits have been executed, the address difference (comparison result) is 5 bits.

The phase difference identifying portion 43b is the phase difference holding portion 42.
Since the allowable phase difference (for example, 8 bits) from b is also added, the comparison result is compared with the allowable phase difference. Since the comparison result is within the allowable range, the identification result is not sent to the phase difference comparison result identifying portion 52 in the timing generation circuit 5.

Therefore, the writing side switching timing and the reading side switching timing are not sent from the generating circuit to the ESM,
The ESM memory size is not switched (memory size remains 8 bits).

That is, when the difference between the write address and the read address after execution is 5 bits, it is within the allowable range of 8 bits, so that the memory size is not switched. Next, when the transmitter 2 is added, the phase comparison part 41b compares the phase of the read timing from the clock supply device 14 and the phase of the write timing from the transmitter 2 to determine the phase difference.
Send to. For example, in the case of FIG. 10 (b), the difference between the write address and the read address is 11 bits.

The phase difference identifying portion 43b has the allowable phase difference of 8 bits from the phase difference holding portion 42b and the comparison result 11 as described above.
The bits are compared, and it is recognized that the comparison result is out of the allowable range, and the identification result is sent to the phase difference comparison result identification portion 52 in the timing generation circuit 5.

The phase difference comparison result identifying part 52 sends a command to the write / read address switching timing generating part 51 to identify that the difference is 11 bits and set the memory size of the ESM to 16 bits.

Since the switching timing generation section 51 has a table (not shown) having an appropriate memory size corresponding to various differences, it is referred to when the write / read timing is input (0 When writing / reading data to / from an address), send the write-side switching timing / read-side switching timing that switches the ESM memory size from 8 bits to 16 bits.

As a result, the memory size of the ESM can be switched to 16 bits without interruption and the ESM can be expanded (see FIG. 10).
(See (c)). The same applies when reducing the memory size.

That is, it is possible to reduce the memory size of the ESM, reduce the amount of hardware, and add lines without affecting other lines while online.

[0077]

As described in detail above, according to the present invention, there is an effect that the circuit scale can be reduced. In addition, it is possible to add lines without affecting other lines while online.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram of an embodiment of first and second aspects of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a main part configuration diagram of another embodiment of the second invention.

FIG. 4 is a configuration diagram of a main part of the third embodiment of the present invention.

FIG. 5 is a configuration diagram of main parts of an embodiment of the fourth present invention.

FIG. 6 is a main part configuration diagram of a fifth embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is a configuration diagram of a main part of another embodiment of the fifth invention.

FIG. 9 is a main part configuration diagram of a sixth embodiment of the present invention.

10 is an explanatory diagram of the operation of FIG.

FIG. 11 is a main part configuration diagram of a conventional example.

12 is an explanatory diagram of the operation of FIG.

[Explanation of symbols]

2a, 2b, 2c Phase monitoring circuit 3 Phase holding circuit 4a Phase comparison circuit 5 Timing generation circuit 11 Transmitter 12 ESM 13 Time switch 14 Clock supply circuit 15 Host device

Front page continuation (72) Inventor Shinji Tajika 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Communication Systems Ltd. (72) Yutaka Asada 3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa No. 18 Fujitsu Communication Systems Limited (72) Inventor Junichi Fujii 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Communication Systems Limited

Claims (6)

[Claims] 1. A reception side clock supply circuit, a first memory, and a first memory, wherein clocks, data, and write timings are transmitted and received through corresponding lines, and a reference frame is generated and supplied to a reception side. In the digital communication device provided with the second memory to which the data read from the memory is written and the control means, the phase difference obtained by comparing the phase of the write timing generated on the transmission side with the phase of the reference timing is The phase difference is divided into a time slot unit phase difference and a remainder phase difference, and the first memory absorbs the phase difference in the remainder and the second memory absorbs the phase difference in the time slot unit. A phase difference absorption method characterized by the above. 2. In the digital communication device, the phase difference obtained by comparing the write timing generated on the transmission side and the phase of the reference timing on the receiving side is calculated as a phase difference for each time slot and a remainder. A first phase monitoring circuit including a phase comparison / absorption amount calculation portion for dividing and transmitting the phase difference and a read timing generation portion is provided, and the read timing generation portion can absorb the residual phase difference input. A read timing of the second memory is generated so as to be transmitted to the first memory, and the control portion controls the read of the second memory so that the phase difference of the input time slot unit can be absorbed. Digital communication equipment. 3. In the digital communication device, the phase monitoring circuit, a phase holding circuit that holds the phase difference detected by the phase monitoring circuit, the phase difference held by the phase holding circuit, and the phase monitoring circuit. When the comparison result is out of the allowable range, it sends a failure notification to the control means and also inserts null information into the frame where the failure notification is sent. 3. The digital communication device according to claim 2, further comprising a circuit. 4. A line connecting the phase holding circuit and the control means is provided, and when the control means detects a failure notification, it sends a phase reset instruction to the phase holding circuit via the line, 4. The digital communication device according to claim 3, wherein the phase holding circuit updates the held phase difference to the phase difference sent by the phase monitoring circuit. 5. A transmission side clock supply circuit for generating and supplying a second memory, control means, and reference timing to a transmission side when transmitting and receiving via lines corresponding to clock, data, and write timing, A second phase monitoring circuit having a phase comparison / absorption amount calculation part for transmitting the phase difference in time slot units among the phase differences obtained by comparing the phases of the reference timing and the read timing transmitted from the receiving side. The receiving side is provided with a first memory to which the data read from the second memory is written and read, and a receiving side clock supply circuit that generates and supplies the read timing, and the control unit The reading control of the second memory is performed so that the phase difference in the input time slot unit can be absorbed, and the receiving side is configured to absorb the remaining phase difference at the read timing. A digital communication device characterized by the above. 6. A digital communication device having a clock supply circuit for transmitting and receiving clock, data, and write timing through corresponding lines, and having a clock supply circuit for generating and supplying read timing and clock on the receiving side. Whether or not the phase comparison result obtained by comparing the phases of the input write timing and the read timing with the first memory having a memory size capable of accommodating a plurality of lines made of lines is within the allowable phase difference range And a phase comparison circuit that sends out an identification result if it is outside the permissible phase difference range, and when the discrimination result is applied, a deviation from the permissible phase difference range is detected and an appropriate built-in table is used. Memory size is determined, and the write side switching timing and the read side switching timing are generated using the write timing and the read timing to generate the first memo. And a timing generation circuit for transmitting the same to the first memory. When the write side switching timing and the read side switching timing are applied, the first memory has a memory size determined by expanding or reducing the write address and the read address. A digital communication device having a switching configuration.