JPH10294722A - Transmission line changeover system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To warrant high transmission line quality by specifying a changeover timing, based on the occurrence of errors and a system selection operation on the occurrence of errors in both systems. SOLUTION: Output signals from buffer memories 8, 9 are outputted as signal, whose phase are match with each other user the control of phase control section 7. The signal are respectively given to error detection sections 12, 13 and buffer memories 10, 11. Based on an error detection result by the error detection sections 12, 13, an error discrimination section 14 produces a selector control signal, that is fed to a selector 15 which selects a 0 system when an error does not exits in a '0' system but exists in only a '1' system or selects the 1 system, when an error does not exist in the 1 system. Then the error discrimination section 14 produces a selector control signal that holds the preceding state without conducting changeovers, when both the 0/1 systems have errors. The selector control signal is given to the selector 15, corresponding to an overhead immediately preceding an error frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention constitutes a high-speed interface unit constituting a 1 + 1 switching system for switching a transmission line in a duplex system, detects a transmission line failure, and performs a forced switching of the transmission line. The present invention relates to a transmission line switching system that enables non-instantaneous switching of a main signal in the event of a failure by adjusting a delay amount due to a path length difference between the 0-system / 1-system at the time of switching, and particularly multiplexes low-speed signals. The present invention relates to a transmission line switching system suitable for a multiplex repeater used for a large-capacity long-distance transmission device that transfers information to a distant place via an inter-station transmission line after generating a high-speed signal.

[0002]

2. Description of the Related Art A multiplex repeater is used for a large-capacity long-distance transmission apparatus that multiplexes a low-speed signal to generate a high-speed signal and then transfers information to a distant place via an inter-station transmission path. The high-speed interface unit of this device constitutes a 1 + 1 switching system. By adjusting the amount of delay due to a difference in path length between the 0 system and the 1 system, the main signal can be switched without interruption during forced switching. It is possible. Further, it has an error detection unit for detecting an error (for example, a B3 error) in the transmission path, and a memory having a storage capacity corresponding to the time required for the error detection processing. It can be performed.

An example of such a conventional switching system for a redundant transmission line is disclosed in Japanese Patent Application Laid-Open No. 5-152939. Japanese Unexamined Patent Publication No. 5-152939 discloses a switching system for a redundant transmission line having a configuration as shown in FIG.

The switching system shown in FIG. 7 uses a CRC (Cycl
ic Redundancy Check) insertion unit 101, signal branching unit 10
2, transmission paths 103 and 104, phase detectors 105 and 10
6, phase control unit 107, buffer memories 108 and 10
9, 110, 111, error detection units 112, 113 and a selector 114.

[0005] CRC insertion section 101 performs a CRC operation on the output signal, and performs overhead (O) of the transmission frame.
Insert the CRC operation value into H). The signal branching unit 102
The main signal into which the CRC operation value is inserted by the CRC insertion unit 101 is branched and transmitted to the transmission paths 103 and 104. One of the transmission lines 103 and 104 is used as an active system, and the other is used as a standby system. Here, for example, the transmission line 103 is assumed to be an active system, and the transmission line 104 is assumed to be a standby system.

[0006] Buffer memories 108 and 109 receive and hold main signals from transmission lines 103 and 104, respectively. Phase detection sections 105 and 106 detect the phase of the main signal input from transmission paths 103 and 104 based on the phase of the overhead byte, and provide the detection result to phase control section 107. Phase control unit 107
Controls the timing at which the main signals are read from the buffer memories 108 and 109 based on the phase detection results of the phase detection units 105 and 106 so that the phases of the two main signals match. Buffer memories 110 and 111
Holds the main signals output from the buffer memories 108 and 109, respectively, gives a delay time of one frame in terms of the frame length of the main signals, and outputs the main signals.

The error detectors 112 and 113 detect CRC errors in the main signals output from the buffer memories 108 and 109, respectively. Selector 11
4 are buffer memories 110 and 111 based on error detection results by the error detection units 112 and 113.
Selects and outputs any one of the main signals output by.

In the configuration shown in FIG. 7, signals received from transmission lines 103 and 104 are
4, a phase difference is generated. The output signals of the buffer memories 108 and 109 are
7 is output as a signal whose phase matches.

Signals read from both buffer memories 108 and 109 are input to error detectors 112 and 113 for detecting errors, respectively, and buffer memories 110 and 111, respectively. Buffer memory 1
10 and 111 output the held main signals after the error detection time has elapsed. The selector 114 that outputs one of the signals read from the buffer memories 110 and 111 is controlled based on the error detection results of the error detectors 112 and 113. In this way, instantaneous interruption switching at the time of transmission line failure is realized without outputting an error frame from the selector 114.

[0010]

Problems to be Solved by the Invention
In the conventional method disclosed in Japanese Patent Publication No.
7, the output signals of the buffer memories 108 and 109 whose phases match each other are output to error detection units 112 and 113 for detecting errors, respectively,
0 and 111 respectively. At this point, the phase difference between the data input from the transmission paths 103 and 104 is absorbed, and the same data is read. After that, the data is held by the buffer memories 110 and 111, and after the time required for the error detection processing has elapsed, the held signal is read and output.

In this method, a selector 114 for selectively outputting one of the signals read from the buffer memories 110 and 111 is controlled based on the error detection results of the error detectors 112 and 113.
By doing so, no error frame is output from the selector 114, and instantaneous interruption switching at the time of a transmission line failure can be realized. However, even in this case, when the frequency of occurrence of errors increases, the probability of outputting an error frame without processing can be increased.

For example, the selector 114 shown in FIG.
Each error signal of the system and the system 1 is input, and FIG.
It is specified that an error-free system is selected and output as shown in FIG. In this case, the selection of the system is switched when the error is detected, and the operation when the error is simultaneously detected in both the systems is not specified. As described above, when an error is detected in both systems at the same time, it is generally conceivable to operate the system so that the system 0 is fixedly selected as shown in FIG. At that time, if the first system has been selected, switching occurs.

As shown in FIG. 9, when errors of the 0-system and 1-system do not occur at the same time but occur alternately, as long as the frequency of occurrence is low, an error frame with "*" added to the output data Can be remedied without mixing.

However, even when the errors of the system 0 and the system 1 occur alternately, if the frequency of occurrence is high, the error remedy is not performed as expected due to the switching timing. For example, as shown in FIG. 10, when the errors of the 0 system and the 1 system occur alternately for each frame, the selection of the system is switched in the middle of the frame when the error is detected, and the arrow of the output data is displayed. Error bits are mixed in the places indicated by.

The present invention has been made in view of the above-mentioned circumstances, and provides a higher transmission path quality by defining a switching timing based on the occurrence of an error and a system selection operation when an error occurs in both systems. It is an object of the present invention to provide a transmission line switching system that can guarantee the above.

[0016]

In order to achieve the above object, a transmission line switching system according to a first aspect of the present invention comprises a first and a second transmission line switching system for detecting an error in a first and a second transmission line, respectively. Based on the error detection results obtained by the first and second error detecting means, and immediately before the data block in which the error occurred in the transmission data of the transmission path, the execution timing of switching to the other transmission path is determined. An error determining unit to be set, and a selector unit to switch and select one of the first and second transmission paths based on the switching execution timing set by the error determining unit.

[0017] The data block of the transmission data in the error determination means may be a data frame.

[0018] The error determination means may include means for setting the switching execution timing to an overhead position immediately before information indicating a head position of a transmission path of a data frame in which an error has occurred.

The error judging means includes means for suppressing the setting of the switching execution timing and preventing the switching when the first and second error detecting means detect an error in the data blocks at the same timing. You may go out.

A transmission line switching system according to a second aspect of the present invention comprises a first and a second memory for storing transmission signals of a first and a second transmission line, respectively, and the first and the second memories. A phase control unit that controls reading of a signal from a memory and matches a phase of a signal read from the first and second memories, and holds a signal read from the first and second memories, respectively, Third and fourth memories for sequentially outputting the hold signal after a predetermined time corresponding to two frames have elapsed, and first and fourth memories for detecting errors in signals read from the first and second memories, respectively. A second error detection unit, an error determination unit that sets a switching execution timing based on the detection of the error in the first and second error detection units,
A selector that selectively outputs one of signals read from the third and fourth memories in accordance with the switching execution timing set by the error determination unit.

[0021] The error determination unit may include means for setting a switching execution timing from the transmission path to the other transmission path immediately before the data block in which the transmission signal error has occurred.

The data block of the transmission signal in the error determination unit may be a data frame.

The error determination unit may include means for setting the switching execution timing to an overhead position immediately before information indicating a head position of a transmission path of a data frame in which an error has occurred.

The error judging section is configured to execute the first and second
The error detecting section may include means for suppressing the setting of the switching execution timing and preventing the switching when the error is detected in the data blocks at the same timing.

In the transmission line switching system according to the present invention, errors in the first and second transmission lines are detected by the first and second error detection means, respectively, and based on the error detection result, the error of the transmission line is detected. Immediately before the data block in which the transmission data error has occurred, the switching execution timing to the other transmission path is set by the error determination means, and based on the switching execution timing, the selector means sets the first and second transmission paths. Is switched and selected. Therefore, the switching timing based on the occurrence of the error is set immediately before the data block in which the error has occurred, and the system selection operation in the case where the error has occurred in both systems is appropriately defined, so that always high transmission path quality can be obtained. Can be

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of a transmission line switching system according to the present invention will be described with reference to FIGS.

FIG. 1 shows a configuration of a transmission line switching system according to an embodiment of the present invention.

The transmission line switching system shown in FIG.
Insertion unit 1, signal branching unit 2, first transmission line 3, second transmission line 4, first phase detection unit 5, second phase detection unit 6, phase control unit 7, first buffer memory 8 , A second buffer memory 9, a third buffer memory 10, a fourth buffer memory 11, a first error detection unit 12, a second error detection unit 13, an error determination unit 14, and a selector 15. .

The CRC insertion unit 1 performs a CRC operation on the signal, and adds C to the overhead (OH) of the transmission frame.
Insert RC operation value. The signal branching unit 2 converts the main signal, into which the CRC operation value has been inserted by the CRC inserting unit 1, into a first transmission path 3
And branches to the second transmission path 4 for transmission. One of the first transmission line 3 and the second transmission line 4 is used as an active system, and the other is used as a standby system. Here, for example, the first transmission line 3 is assumed to be an active system, and the transmission line 4 is assumed to be a standby system.

The first buffer memory 8 and the second buffer memory 9 are connected to the first transmission path 3 and the second transmission path 4
And receives and holds the main signal. The first phase detector 5 and the second phase detector 6 detect the phase of the main signal input from the first transmission path 3 and the second transmission path 4 based on the phase of the overhead byte, respectively. The detection result is provided to the phase control unit 7.

The phase controller 7 performs the first phase detection based on the phase detection results of the first phase detector 5 and the second phase detector 6.
The timing of reading the main signal from each of the buffer memory 8 and the second buffer memory 9 is controlled so that the phases of the two main signals match. The third buffer memory 10 and the fourth buffer memory 11 hold the main signal output from the first buffer memory 8 and the second buffer memory 9, respectively, and convert the main signal into a frame length of 2 in the main signal.
The main signal is output with a delay time corresponding to a frame.

The first error detector 12 and the second error detector 13 detect CRC errors in the main signals output from the first buffer memory 8 and the second buffer memory 9, respectively. The error determination unit 14
The switching condition is determined based on the error detection results of the error detection unit 12 and the second error detection unit 13 described above. The selector 14 controls the third buffer memory 10 and the fourth buffer memory 10 based on the determination result of the switching condition by the error determination unit 14.
One of the main signals output from the buffer memory 11 is selected and output.

As shown in FIG. 2, the error determination unit 14
A first delay circuit 21, a second delay circuit 22, a switching condition determination circuit 23, and a flip-flop 24 are provided.

The first delay circuit 21 delays the error detection signal provided from the first error detector 12 for a predetermined time. The second delay circuit 22 includes the second error detection unit 13
Is delayed by a predetermined time.
The switching condition determination circuit 23 includes a 0-system error signal and a 1-system error provided from the first error detection unit 12 and the second error detection unit 13 via the first delay circuit 21 and the second delay circuit 22, respectively. The switching condition is determined based on the signal.

That is, the switching condition determination circuit 23 is configured as shown in FIG.
As shown in (1), when there is no system 0 error and there is a system 1 error, a selector control signal for switching to system 0 is generated, and when there is a system 0 error and there is no system 1 error, a selector control signal for switching to system 1 is generated. . When there is no both the 0-system error and the 1-system error and when there are both the 0-system error and the 1-system error, the switching is not performed and the selector control signal for maintaining the previous state is generated. The selector control signal output from the switching condition determination circuit 23 is provided to a terminal D of the flip-flop 24.

The flip-flop 24 outputs a selector control signal output from the switching condition determination circuit 23 to, for example, a third
Buffer memory 10 and fourth buffer memory 11
In synchronization with the overhead pulse given to terminal C based on the output overhead of
To control the selector 15.

At this time, the first delay circuit 21 and the second
The delay circuit 22 of the first error detection unit 12 and the second error detection unit 13 performs the time required for synchronizing the condition determination operation of the switching condition determination circuit 23 and the switching operation of the selector 15 with the overhead pulse. It is provided to delay the error detection signal.

Next, the operation of the transmission line switching system shown in FIGS. 1 and 2 will be described.

The CRC insertion value is inserted in the CRC insertion unit 1, the signal is branched in the signal branching unit 2, and the signal received through the first transmission line 3 and the second transmission line 4 includes the first transmission line. A phase difference occurs due to a difference in path length between the path 3 and the second transmission path 4. The output signals of the first buffer memory 8 and the second buffer memory 9 are output as signals whose phases match under the control of the phase controller 7.

The signals read from the first buffer memory 8 and the second buffer memory 9 are divided into a first error detector 12 and a second error detector 13 for detecting an error, and a third buffer memory 10 respectively. And the fourth buffer memory 11. The third buffer memory 10 and the fourth buffer memory 11 are:
After the error detection processing time has elapsed, the held main signal is output. The error determination section 14 is controlled based on the error detection results of the first error detection section 12 and the second error detection section 13.

The error determination section 14 delays the error detection results of the first error detection section 12 and the second error detection section 13 by a first delay circuit 21 and a second delay circuit 22, respectively, for a required time. To the switching condition determination circuit 23.

As shown in FIG. 3, the switching condition determination circuit 23
When there is no 0-system error and only the 1-system error exists, a selector control signal for switching to the 0-system, and when there is only the 0-system error, and when there is no 1-system error, switching to the 1-system is generated. The switching condition determination circuit 23 outputs a selector control signal that does not perform switching and retains the previous state when there is no both the 0-system error and the 1-system error and when there is both the 0-system error and the 1-system error. For example, it is generated as a high impedance output in three-state logic. This selector control signal is supplied from the switching condition determination circuit 23 to the terminal D of the flip-flop 24.

The flip-flop 24 supplies the selector control signal output from the switching condition determination circuit 23 to the terminal C based on, for example, the output overhead of the third buffer memory 10 and the fourth buffer memory 11. In synchronization with the overhead pulse corresponding to the overhead just before the error frame, the selector 15
To control the selector 15.

The selector 15 outputs one of the signals read from the third buffer memory 10 and the fourth buffer memory 11 according to the selector control signal output from the flip-flop 24 of the error determination unit 14. Select and output one.

That is, the transmission line switching system shown in FIGS. 1 and 2 has an error determination section 14 for generating a selector control signal at a timing corresponding to the overhead immediately before the error frame. The switch just before is executed.

More specifically, as shown in FIG. 4, by specifying the execution position of the switching due to the detected error in the overhead immediately before the so-called J1 byte indicating the head position of the path, both the 0-system and the 1-system are specified. Even when the frequency of errors occurring in the system is high, it is possible to select an error-free frame. Further, when an error occurs in both the 0-system and the 1-system, the switching control of the selector 15 is prevented to prevent useless and careless switching and prevent error bits from being output. .

The operation of the transmission line switching system shown in FIGS. 1 and 2 will be described in more detail with reference to FIGS.

As shown in FIG. 4, even when the frequency of errors occurring in both the 0-system and the 1-system is high, in order to select a frame having no error, the execution timing of the switching by the error detection is set to the error frame. Stipulated immediately before That is, the error detection signals in the first error detection unit 12 and the second error detection unit 13 are transmitted to the first delay circuit 2
The first and second delay circuits 22 delay the required time to correspond to the overhead position immediately before the J1 byte indicating the head position of the path of each frame.

As shown in FIG. 5, when an error is detected in the same frame in both the system 0 and the system 1, no matter which system is selected by the selector 15, the error frame is output from the selector. Will be done. In such a case, control of the selector is not performed, unnecessary switching is prevented, and occurrence of an error or the like due to switching is prevented.

Further, when an error occurs alternately for each frame in the 0-system and the 1-system, an error bit is output as shown in FIG. 10 in the conventional system. In the transmission line switching system shown in FIG. 6, error bits can be relieved as shown in FIG. That is, even if an error occurs alternately for each frame in the 0-system and the 1-system, since the switching timing is the overhead immediately before the error frame, a part of the error frame is output as in the case of FIG. And only normal data frames are output.

The transmission line switching system of the present invention
It can be realized by using a normal computer system without configuring as a dedicated system. For example, a medium (floppy disk, C) storing a program for executing the above-described operation in a computer system.
By installing the program from a D-ROM or the like, a transmission line switching system that executes the above-described processing can be constructed. By installation, the program is stored in a medium such as a hard disk in the computer system to configure a transmission line switching system,
Provided for execution.

The medium for supplying the program to the computer is not limited to a storage medium in a narrow sense, but may be a communication line,
Like a communication network and a communication system, it may be a storage medium in a broad sense including a communication medium that temporarily and fluidly stores information such as a program.

For example, the program may be registered in an FTP (File Transfer Protocol) server provided on a communication network such as the Internet, and may be distributed to an FTP client via the network. The program may be registered in a board system or the like and distributed via a network. Then start this program and run the OS
The above processing can be achieved by executing under the control of the (Operating System). Furthermore, the above-described processing can also be achieved by starting and executing the program while transferring the program via the communication network.

[0055]

As described above, in the transmission line switching system according to the present invention, errors in the first and second transmission lines are detected by the first and second error detection means, respectively, and the error detection result is obtained. Based on the above, immediately before the data block in which the error of the transmission data of the transmission path has occurred, the switching execution timing to the other transmission path is set by the error determination means, and based on the switching execution timing, the selector means One of the first and second transmission paths is switched and selected. Therefore, the switching timing based on the occurrence of the error is set immediately before the data block in which the error has occurred, and the system selection operation when an error has occurred in both systems is appropriately defined.

That is, according to the present invention, by specifying the timing of switching based on the occurrence of an error and the system selection operation when an error occurs in both systems, transmission line switching that can guarantee higher transmission line quality is achieved. A system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a transmission line switching system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an error determination unit in the transmission line switching system of FIG. 1 in detail.

FIG. 3 is a diagram for explaining an operation of a switching condition determining unit of an error determining unit in the transmission line switching system of FIG. 1;

FIG. 4 is a timing explanatory diagram for explaining an operation exhibiting an effect by setting a switching timing in the transmission line switching system of FIG. 1;

FIG. 5 is an explanatory timing chart for explaining an operation that exerts an effect by controlling switching conditions in the transmission line switching system of FIG. 1;

FIG. 6 is a timing explanatory diagram for explaining a further operation exhibiting an effect by setting a switching timing in the transmission line switching system of FIG. 1;

FIG. 7 is a block diagram illustrating a configuration of an example of a conventional switching system.

FIG. 8 is a diagram for explaining an operation of a selector of an error determination unit in the switching system of FIG. 7;

9 is an explanatory timing chart for explaining an operation when an error rescue effect is obtained in the switching system of FIG. 7;

10 is an explanatory timing chart for explaining an operation in the case where an error rescue effect cannot be obtained in the switching system of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CRC insertion part 2 Signal branch part 3, 4 Transmission line 5, 6 Phase detection part 7 Phase control part 8, 9, 10, 11 Buffer memory 12, 13 Error detection part 14 Error judgment part 15 Selector 21, 22 Delay circuit 23 Switching condition judgment circuit 24 flip-flop

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Haruhiko Tanimoto 3-18-21 Shibaura, Minato-ku, Tokyo Inside NEC Engineering Co., Ltd.

Claims (9)

[Claims] 1. A first and a second error detecting means for detecting an error in a first and a second transmission path, respectively, based on an error detection result by the first and the second error detecting means. Error determining means for setting a switching execution timing to the other transmission path immediately before a data block in which an error has occurred in transmission data of the path; and the first and second switching means based on the switching execution timing set by the error determination means. Selector means for switching and selecting one of the two transmission paths. 2. The transmission line switching system according to claim 1, wherein the data block of the transmission data in the error determination unit is a data frame. 3. The apparatus according to claim 2, wherein said error determination means includes means for setting said switching execution timing to an overhead position immediately before information indicating a head position of a transmission path of a data frame in which an error has occurred. 2. The transmission path switching system according to 1. 4. The error judging means, when the first and second error detecting means detects an error in a data block at the same timing, suppresses the setting of the switching execution timing and prevents the switching. The transmission line switching system according to any one of claims 1 to 3, further comprising: 5. A first and a second memory for respectively storing transmission signals of a first and a second transmission line, and controlling reading of signals from the first and the second memories, And a phase control unit for matching the phases of the signals read from the second memory, and holding the signals read from the first and second memories, respectively, and after elapse of a predetermined time corresponding to at least two frames, Third and fourth memories that sequentially output the holding signal; first and second error detectors that detect errors of signals read from the first and second memories, respectively; An error determining unit that sets a switching execution timing based on the detection of the error in the error detecting unit, and according to the switching execution timing set by the error determining unit. Serial third and fourth transmission path switching system characterized by comprising a selector, a for selectively outputting either one of the signal read from the memory of the. 6. The apparatus according to claim 1, wherein the error determination unit includes means for setting a switching execution timing from the transmission path to the other transmission path immediately before the data block in which the transmission signal error has occurred. 6. The transmission line switching system according to 5. 7. The transmission line switching system according to claim 6, wherein the data block of the transmission signal in the error determination unit is a data frame. 8. The apparatus according to claim 7, wherein said error determination unit includes means for setting said switching execution timing to an overhead position immediately before information indicating a head position of a transmission path of a data frame in which an error has occurred. 2. The transmission path switching system according to 1. 9. The error judging unit, when the first and second error detecting units detect an error in a data block at the same timing, suppresses the setting of the switching execution timing and prevents the switching. The transmission line switching system according to any one of claims 5 to 8, comprising: