JPH11205267A - Uninterruptible switching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an uninterruptible switching system without limiting a path length difference permitted for uninterruptible switching that realizes uniterruptible switching compatible with asynchronous data and uninterruptible switching for data not adopting a frame configuration. SOLUTION: A transmission section 11 provides an output without adding an identification signal to a POH of an input signal. A B3 byte separation/ comparison section 29 separates a B3 byte and compares the input signals, retrieves a frame with the same value in 0 and 1 systems, and a frame difference is detected. A 0 system frame aligner 23 and a 1 system frame aligner 24 apply write/read control to a memory of main signal data. A read-out control section 26 determines frame difference information by seeking parts where B3 byte are coincident to determine a read-out phase of the 0 system frame aligner 23 and the 1 system frame aligner 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hitless switching system, and more particularly to a large-capacity long-distance switching system that multiplexes low-speed signals to generate high-speed signals and then transfers information to a distant location via an inter-station transmission path. The present invention relates to a distance transmission device.

[0002]

2. Description of the Related Art Conventionally, in a large-capacity long-distance transmission apparatus of this kind, after multiplexing a low-speed signal and then generating a high-speed signal, information is transferred to a distant place via an inter-station transmission line. Like that.

[0003] The high-speed interface section of this apparatus constitutes a 1 + 1 switching system. By adjusting the amount of delay due to the difference in path length between the system 0 path and the system 1 path, it is possible to switch the main signal without instantaneous interruption at the time of forced switching.
Further, a memory for a failure detection time and a transmission path B3 error detection circuit are provided, and by detecting a transmission path failure, instantaneous interruption switching at the time of failure is enabled.

FIG. 8 shows a principle diagram of a conventional transmission line instantaneous interruption switching method. In this figure, the transmitting device 3 includes a transmitting unit 31 and an identification signal inserting unit 32, and the receiving device 4 includes a 0-system receiving unit 41, a 1-system receiving unit 42,
System frame aligner 43 and 1 system frame aligner 44
, Identification signal (Z3) separation unit 45, and read control unit 46
And a selector 47.

[0005] The transmitting section 31 is provided with an OH (Over Head:
Overhead) addition and multiplexing, E / O (Electri)
cal / Optical) conversion, etc.
(Path Over Head: Path overhead)
To the identification signal.

The 0-system receiving unit 41 and the 1-system receiving unit 42
It has functions such as E conversion, separation, and OH termination, and performs a write phase instruction and a stuff instruction to the 0-system frame aligner 43 and the 1-system frame aligner 44 according to the reception pointer value.

The 0-system frame aligner 43 and the 1-system frame aligner 44 control writing and reading of main signal data to and from a memory (not shown). The identification signal separation unit 45 separates the identification signals from the data of the 0-system and the 1-system, and detects the frame difference by comparing the identification signals of the 0-system and the 1-system.

The read controller 46 determines the read phases of the 0-system frame aligner 43 and the 1-system frame aligner 44 from the frame difference information. The selection unit 47 has a selector (not shown), and executes instantaneous interruption switching between the 0 system and the 1 system.

The identification signal insertion unit 32 sends an STM (Sync)
(Hronous Transfer Mode: Synchronous Transfer Mode) The identification signal sent to an arbitrary byte of the POH signal in the frame format is separated and read by the identification signal separation unit 45 that inputs the 0-system data 221 and the 1-system data 225.

When the frame difference is detected by the identification signal separating section 45, the read frames 232 and 233 at the timings advanced by the frame difference from the read control section 46 are sent to the 0-system frame aligner 43 and the 1-system frame aligner 44, respectively. After synchronizing the frames of the read data 229 and 230, the selector 47 is switched.

The above method is based on the new synchronous network SDH (Synch).
ronous Digital Hierarchy:
Synchronous Digital Hierarchy) It is an object of the present invention to provide a transmission path non-stop switching method that enables non-stop switching of data between two transmission paths irrespective of distance in switching of a duplex transmission path of a digital multiplex transmission system. .

In this method, the POH (Z3) is used as an identification signal, and the receiving side detects the frame phase difference between the system 0 and the system 1 to realize instantaneous interruption switching. This method is disclosed in JP-A-6-132944.

As a general system for instantaneous interruptionless switching, there is a transmission line instantaneous interruption switching method as shown in FIG.
10, the transmitting device 5 includes a transmitting unit 51 and an identification signal inserting unit 52. The receiving device 6 includes a 0-system receiving unit 61, a 1-system receiving unit 62, and a 0-system frame aligner 6.
3, the first system frame aligner 64, and the identification signal (J1)
It includes a separation unit 65, a read control unit 66, and a selection unit 67.

According to this method, data of a multi-frame configuration can be switched instantaneously without interruption using POH (J1) as an identification signal. These methods are common in using an identification signal added on the transmission side.

The phase matching operation in the case of an N multi-frame configuration according to these methods is as shown in FIG. As shown in FIG. 11, the phase adjustment for the instantaneous interruption switching is performed by the data phase difference of the 0 system and the 1 system + DLY (Dela (Dela)).
y) The delay can be realized by setting a (margin) delay in the read phase.

[0016]

The above-mentioned conventional hitless switching method has the following problems in consideration of hitless switching of asynchronous data. First, considering the transmitting device, when a method of inserting an identification signal into a byte in a POH is adopted, an asynchronous signal is input to the transmitting device, and an arbitrary byte of the POH is rewritten based on a clock in the device. A method is generally used. in this case,
The stuffing operation is continued by the input signal, and it becomes difficult to overwrite the POH with the same number when it is shifted by one frame or more.

In the instantaneous interruption switching system corresponding to the asynchronous signal, a system that does not rely on the identification signal on the transmission side is safe.
The operation of the transmission-side device in the conventional transmission path non-stop switching method shown in FIG. 8 is as shown in FIG.

That is, FIG. 9A shows an initial state,
No. is assigned to POH1 according to the counter value of the internal clock.
1 indicates a state of being overwritten. FIG. 9B shows FIG.
(A) shows a state in which the stuff is delayed by フ レ ー ム frame due to the stuff. 1 indicates a state of being overwritten.

FIG. 9C shows a state in which the state shown in FIG. 9B is further delayed by 1/2 frame by the stuff, and the state shown in FIG. 9A is delayed by one frame. No. is assigned to POH1 by the counter value. 2 indicates a state of being overwritten. In this case, a data error occurs on the receiving side.

That is, the N of the identification signal added to the POH
o. Is determined by the value of the counter in the apparatus, and FIG.
When the POH added in (a) is moved by the staff to FIG. Is shifted by one, and the receiving unit is temporarily out of synchronization.

Considering the receiving apparatus, the conventional example has a frame aligner for each of the 0-system and the 1-system of the receiving apparatus, and reads out data stored in the internal memory corresponding to the stuff amount of input data. Control is performed based on the internal clock. That is, it seems that the read phase is always fixed.

In this method, the amount of stuff is small even for asynchronous data, and can be dealt with only when the stuff amount fluctuates within a certain range. However, when the write phase exceeds the read phase due to continuous stuff operation, Can't respond. A function for changing the output phase is required in response to a stuff request using the result of comparison between the write address and the read address of the memory.

Further, considering the distance limit that can be switched without instantaneous interruption, in the conventional method, when switching the duplex transmission line of the new synchronous network SDH digital multiplex transmission system, the instantaneous transmission of data between two transmission lines regardless of the distance is performed. It is an object of the present invention to provide a transmission path non-interruptible switching method that enables disconnection switching. However, in a method of identifying a phase difference using an arbitrary byte of a POH, a distance difference at which instantaneous non-interruptible switching can be performed depends on the identification signal. This depends on the configuration of the multi-frame. In the case of the conventional example, the number of frames is ²⁸ minutes.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a method of instantaneous interruption switching corresponding to asynchronous data and data of non-multi-frame data without limiting the path length difference capable of instantaneous interruption switching. It is an object of the present invention to provide an instantaneous interruption switching system capable of realizing instantaneous interruption switching.

[0025]

According to the present invention, there is provided a non-interruptible switching system according to the present invention, wherein a transmission side device and a reception side device are connected to each other by a first route and a second route. An instantaneous interruption switching system for performing instantaneous interruption switching with the second path, wherein first reception data received via the first path and second reception data received via the second path. Detecting means for detecting a match / mismatch with the received data, and the first means until the detecting means detects a match.
And a shift unit that shifts at least one of the received data and the second received data.

That is, the hitless switching system of the present invention realizes hitless switching by comparing received data at a receiving device without inserting an identification signal into a POH at a transmitting device. Achieve phase matching.

More specifically, by using the B3 byte in the POH of the received data, it is possible to simply detect the match / mismatch between the data of the system 0 and the system 1 and shift the data until the data match. Realize instantaneous interruption switching.

Further, the configuration is such that stuff can be handled without fixing the output phase of the phase matching memory.
As a result, it is possible to realize instantaneous interruption switching of data that does not have a multi-frame configuration, without limiting the path length difference that allows instantaneous interruption switching.

[0029]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a hitless switching system according to an embodiment of the present invention. In the figure, the transmitting device 1 of the hitless switching system according to one embodiment of the present invention includes a transmitting unit 11.

The receiving side device 2 includes a 0-system receiving unit 21,
1-system receiving unit 22, 0-system frame aligner 23, 1-system frame aligner 24, transmission stuff detecting unit 25,
The read control unit 26 and the 0-system transmission pointer insertion unit (PTR
An INS (Pointer Insert) 27, a 1-system transmission pointer insertion unit (PTR INS) 28, a B3 byte separation / comparison unit 29, and a selection unit 30 are provided.

The transmitting unit 11 transmits an OH (Over Head:
Overhead) addition and multiplexing, E / O (Electri)
It has functions such as cal / optical conversion and does not require the addition of an identification signal to a POH (Path Over Head: path overhead) as in the conventional example.

The 0-system receiving unit 21 and the 1-system receiving unit 22 are
It has functions such as E conversion, separation, and OH termination, and performs a write phase instruction and a stuff instruction to the 0-system frame aligner 23 and the 1-system frame aligner 24 according to the reception pointer value. The B3 byte separation / comparison unit 29 stores the B3
The bytes are separated and compared, and a frame having the same value in the 0 system and the 1 system is searched to detect a frame difference.

The 0-system frame aligner 23 and the 1-system frame aligner 24 control writing and reading of main signal data to and from a memory (not shown). Transmission staff detection unit 2
5 compares the write phase with the read phase and changes the read when those phases are closer or farther than specified [P
(Positive) stuff / N (negative) stuff instruction], a new pointer value is generated, and the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 change the pointer value.

The reading control unit 26 continues to operate the counter (0 system) (not shown) or the counter (1) until the B3 byte matches.
The LOAD value of the (system) (not shown) is changed, the frame difference information is determined by searching for a match, and the read phases of the 0-system frame aligner 23 and the 1-system frame aligner 24 are determined.

The 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 perform pointer replacement. The selection unit 30 has a selector (not shown), and executes zero-interruption switching between the 0 system and the 1 system.

FIG. 2A is a diagram showing a phase matching operation according to one embodiment of the present invention, and FIG. 2B is a diagram showing a state at the time of completion of phase matching according to one embodiment of the present invention. The operation of the instantaneous interruption switching system according to one embodiment of the present invention will be described with reference to FIGS.

In the instantaneous interruption switching system, the receiving unit 2 receives the 0-system data 112 and the 1-system data 113 which are branched by the transmitting unit 11 of the transmitting apparatus 1 and pass through different transmission paths. I do.

In the receiving side device 2, the data 121 and 12 received by the 0-system receiving unit 21 and the 1-system receiving unit 22, respectively.
2 is written to the 0-system frame aligner 23 and the 1-system frame aligner 24, respectively.

The reading of data from the 0-system frame aligner 23 and the 1-system frame aligner 24 is performed by a read control unit 26.
Readout frame (default value) 139 controlled by
In accordance with 140, the reading is performed at the 0-system read phase and the 1-system read phase, respectively.

From the data 135 and 136 read from the memories (not shown) of the 0-system frame aligner 23 and the 1-system frame aligner 24, the B3 byte is extracted by the B3 byte separating / comparing unit 29, and the B3 bytes are obtained. Are compared.

In this case, when the comparison result of the B3 bytes does not match, the read phase of the memory is delayed by another frame and the B3 bytes are compared again. In this way, by comparing the B3 bytes with the B3 byte separating / comparing unit 29, it is possible to easily confirm the coincidence of the data [see FIG. 2A].

If the comparison result in the B3 byte separation / comparison section 29 does not match, the read control section 26 sets the read frame 13
One of the data read phases 9 and 140 is delayed by one frame, and the B3 byte separation / comparison unit 29 again compares the B3 bytes of the data 135 and 136 from the 0-system frame aligner 23 and the 1-system frame aligner 24, respectively.

By repeating the above comparison operation, B3
When the bytes match, the multi-frame continuous match is checked for protection and the current read phase is fixed, so that phase matching for instantaneous interruption switching can be realized [FIG. 2 (b). reference].

If the B3 bytes do not match in the above operation, the reference system is reversed.
By repeating the comparison operation in the byte separation / comparison section 29, a match of the B3 byte is searched.

FIG. 3 shows the B3 byte separating / comparing unit 29 of FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In the figure, the B3 byte separation / comparison unit 29 outputs a B3DET (B3 Detect).
or) 29a, 29b and COMP (Comparat)
or) 29c and a frame protection circuit 29d.

The B3 byte separation / comparison section 29 uses the B3DE
The B3 bytes separated by T29a and 29b are COM
The comparison is made at P29c, and 0 is set by the frame protection circuit 29d.
A frame having the same value is searched in the system and the system 1, and a frame difference is detected. Here, the B3 byte is used for monitoring the quality of the path, and the BIP (Bit In Parity) is used.
y) The calculation result of -8 is transmitted.

FIG. 4 is a block diagram showing a configuration of the read control unit 26 of FIG. In the figure, the read control unit 26 includes a difference control circuit 26a, a counter (0 system) 26b, and a counter (1 system) 26c.

The difference control circuit 26a operates the counter (0-system) 26b or the counter (1) until the B3 byte matches.
System) Change the LOAD value of 26c and determine the frame difference information by searching for a match.
Frame aligner 23 and 1 frame aligner 24
Is determined. Here, the counter (0 system) 2
6b and the counter (system 1) 26c are operated by the internal clock.

FIG. 5 shows the 0-system frame aligner 23 and the 1-system frame aligner 24 of FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In the figure, the configuration of the 1-system frame aligner 24 is
And the description is omitted.

The 0-system frame aligner 23 includes a write control circuit 23a, a frame memory 23b, and a phase control circuit 23.
and a read control circuit 23d. The transmission stuff detection unit 25 includes a stuff detection circuit 25a and a new pointer (PTR) value generation circuit 25b.

In the 0-system frame aligner 23 and the 1-system frame aligner 24, write control circuits 23a and 24a (write control circuit 24a is not shown) and read control circuits 23d and
The control of writing and reading of the main signal data to and from the frame memories 23b and 24b (the frame memory 24b is not shown) is performed by 24d (the read control circuit 24d is not shown). The phase control circuits 23c and 24c
read control circuits 23d, 23d based on the write phases of
4d read phase is controlled.

The stuff detection circuit 25a includes the write control circuit 2
3a and 24a and read control circuits 23d and 24
d with the readout phase and changes the readout when those phases are closer or farther than specified (P stuff / N
Staff instructions). At this time, the new pointer value generation circuit 25
b generates a new pointer value, and the 0-system transmission pointer insertion unit 2
The pointer value is changed by the 7 and 1 system transmission pointer insertion unit 28.

Here, the transmission pointer processing will be described. In the transmission stuff unit 25, the frame memories 23b and 2
4b, the write address and the read address are compared on a frame-by-frame basis, and when they approach a threshold or more, the 0-system frame aligner 23 and the 1-system frame aligner 24 and the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28
And sends a staff request.

At this time, the 0-system frame aligner 23 and the 1-system frame aligner 24 change the memory output address and output data. The 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 change the transmission pointer value.

The stuff amount of the pointer is the same as that of the source data, and there is no significant difference between the 0 system and the 1 system.
The configuration is such that the stuff amount is determined based on the system or the system 1, so that the pointer values of both systems are the same.

FIG. 6A is a block diagram showing the configuration of the 0-system transmission pointer insertion section 27 of FIG. 1, and FIG. 6B is a diagram showing the format of the pointer (H1, H2 bytes). In FIG. 6A, the 0-system transmission pointer insertion unit 2
7 is a pointer pulse (PTRPLS: Pointer)
(Pulse) generation circuit 27a and pointer replacement unit 2
7b.

The pointer pulse generation circuits 27a and 27a of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28
28a (a pointer pulse generation circuit 28a is not shown) generates a pointer pulse in response to a stuff request, and sends the pointer pulse to the pointer replacement units 27b and 28b (the pointer replacement unit 28b is not shown) to generate a new pointer pulse. Indicate the position to change the price.

The pointer replacement units 27b and 28b perform replacement of a new pointer value to a position designated by the pointer pulse generation circuits 27a and 28a. In this case, at the time of the P staff, the next byte of the H3 byte is treated as OH,
H3 bytes are treated as payload when N stuffs are used.
In FIG. 6B, NDF is a new data flag.

FIG. 7A is a diagram showing the operation of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 of FIG. 1 during P stuffing, and FIG. N of the transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28
It is a figure showing operation at the time of a staff.

In these figures, the data IN is stored in a 0-system transmission pointer insertion unit 27 and a 1-system transmission pointer insertion unit 28.
Shows data transmitted from the 0-system frame aligner 23 and the 1-system frame aligner 24, and the data OUT is 0.
The data transmitted by the system transmission pointer insertion unit 27 and the system 1 transmission pointer insertion unit 28 after rewriting the OH portion of the data IN in accordance with the pointer pulse are shown.

The previous frame shown in FIG. 7A shows the operation of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 when the pointer value A = 2 when there is no stuff operation. Here, the pointer value A is a numerical value indicating the head position of the path, and the J1 byte that is the POH identification signal is S
DH (Synchronous Digital Hi)
erarchy: indicates the position on the frame format of synchronous digital hierarchy.

FIG. 7A shows the operation of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 when a stuff operation occurs. The 0-system frame aligner 23 and the 1-system frame aligner 24 perform data reading by OH
The output is delayed by one byte.

Therefore, the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 overwrite the OH portion of the input data IN with OH by one byte in accordance with the pointer pulse. Therefore, the pointer value of the data OUT becomes the pointer value A + 1 = 3, and the pointer value is changed by the P stuff.

The previous frame shown in FIG. 7B shows the operation of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 when the pointer value A = 2 when there is no stuff operation.

The N stuff shown in FIG. 7B shows the operation of the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 when a stuff operation occurs. The 0-system frame aligner 23 and the 1-system frame aligner 24 perform data reading by OH
Output one byte forward at the part.

Therefore, the 0-system transmission pointer insertion unit 27 and the 1-system transmission pointer insertion unit 28 overwrite the OH part of the input data IN with OH by reducing the byte by one byte according to the pointer pulse. Therefore, data OU
The pointer value of T becomes the pointer value A-1 = 1, and the pointer value is changed by N stuff.

As described above, the input signal 11
The identification signal is transmitted to the receiving device 2 without inserting the identification signal into the 1 POH, and the B3 byte separating / comparing unit 29 of the receiving device 2 separates and compares the B1 byte from each of the 0-system and 1-system received data. Thus, the frames having the same value in the 0-system and the 1-system are searched to detect the frame difference between them, and the read control unit 26 searches for a match of the B3 byte to determine the frame difference information. By determining the read phases of the aligner 23 and the 1-system frame aligner 24, phase matching for realizing instantaneous interruption switching is realized.

More specifically, the B3 byte separating / comparing unit 29 simply uses the B3 byte in the POH to easily associate the 0-system with the 1-system.
By detecting the match / mismatch of the data with the system and shifting the data by the read control unit 26 until the match, the instantaneous interruption switching is realized.

Further, the configuration is such that stuff can be handled without fixing the output phase of the phase matching memory.
As a result, it is possible to realize instantaneous interruption switching of data that is not in a multi-frame configuration without limiting the path length difference that can be instantaneously switched.

Therefore, the instantaneous interruption switching corresponding to asynchronous data and the instantaneous interruption switching of data having no multi-frame configuration can be realized without limiting the path length difference that can be instantaneously switched.

[0071]

As described above, according to the present invention, in a transmission system in which a transmitting apparatus and a receiving apparatus are connected by a 0-system path and a 1-system path, a 0-system path and a 1-system path are used. In the non-interruptible switching system for performing non-instantaneous interruption switching between the first system and the second system, the receiving device receives the 0-system received data received via the 0-system route and the 1-system received data received via the 1-system route. Is detected, and at least one of the 0-system received data and the 1-system received data is shifted until the coincidence is detected, thereby limiting the path length difference that can be switched without instantaneous interruption. Without this, there is an effect that instantaneous interruption switching corresponding to asynchronous data and instantaneous interruption switching of data having no multi-frame configuration can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a hitless switching system according to an embodiment of the present invention.

2A is a diagram illustrating a phase matching operation according to one embodiment of the present invention, and FIG. 2B is a diagram illustrating a state at the time of completion of phase matching according to one embodiment of the present invention;

FIG. 3 is a block diagram illustrating a configuration of a B3 byte separating / comparing unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a read control unit in FIG. 1;

5 is a block diagram showing a configuration of a 0-system frame aligner and a 1-system frame aligner of FIG. 1 and a transmission stuff detector.

6A is a block diagram showing a configuration of a 0-system transmission pointer insertion unit in FIG. 1, and FIG. 6B is a diagram showing a format of a PTR (H1, H2 bytes).

FIG. 7 (a) is a diagram illustrating the 0-system transmission pointer insertion unit and 1 shown in FIG. 1;
The figure showing the operation at the time of P stuff of the system transmission pointer insertion unit,
FIG. 2B is a diagram illustrating the operation of the 0-system transmission pointer insertion unit and the 1-system transmission pointer insertion unit of FIG. 1 at the time of N stuffing.

FIG. 8 is a block diagram illustrating a configuration example of a hitless interruption switching system according to a conventional example.

FIG. 9 is a diagram illustrating an operation of the transmission unit in FIG. 8;

FIG. 10 is a block diagram showing another configuration example of the hitless interruption switching system according to the conventional example.

FIG. 11 is a diagram showing a phase matching operation of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmitting apparatus 2 Receiving apparatus 11 Transmitting unit 21 0-system receiving unit 22 1-system receiving unit 23 0-system frame aligner 23a Write control circuit 23b Frame memory 23c Phase control circuit 23d Read control circuit 24 1-system frame aligner 25 Transmission staff Detection unit 25a Staff detection circuit 25b New pointer value generation circuit 26 Read control unit 26a Difference control circuit 26b Counter (0 system) 26c Counter (1 system) 27 0 system transmission pointer insertion unit 27a Pointer pulse generation circuit 27b Pointer replacement unit 28 1 System transmission pointer insertion unit 29 B3 byte separation / comparison unit 29a, 29b B3DET 29c COMP 29d Frame protection circuit 30 Selection unit

Claims (4)

[Claims] 1. A transmission system in which a transmission-side device and a reception-side device are connected via a first path and a second path, and perform non-instantaneous switching between the first path and the second path. A momentary interruption switching system, comprising: detecting means for detecting a match / mismatch between first received data received via the first path and second received data received via the second path. Until the detecting means detects a match.
And a shift unit for shifting at least one of the received data and the second received data in the receiving-side device. 2. The method according to claim 1, wherein the detecting unit separates and compares a B3 byte of a predetermined pattern from a path overhead of each of the first reception data and the second reception data, and performs the first reception based on a comparison result. Searching means for searching for a frame in which the received data and the second received data have the same value;
2. The system according to claim 1, further comprising means for detecting a frame difference between the frames searched by said search means. 3. The receiving apparatus includes first and second storage means for storing the first received data and the second received data, respectively, and the shift means shifts when a mismatch is detected by the detecting means. 3. The system according to claim 1, wherein said means delays data reading from one of said first and second storage means. 4. When a match is detected by the detection means, a multi-frame continuous match is confirmed for protection to protect the first frame.
4. The system according to claim 3, further comprising means for fixing a current read phase of the second storage means.