JP2000324072A - Pointer termination part and uninterruptive switching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve uninterruptive switching by simpler hardware constitution by allowing a readout timing generation part to stop a readout and shift readout timing to a pointer insertion part only for a pulse output section. SOLUTION: A pointer detection part 21 detects a pointer byte of an SDH signal received from an active or standby transmission line, and extracts and passes its value to a frame header generation part 25. The frame header generation part 25 finds the head of a virtual container VC signal from the pointer value received from the pointer detection part 21 and generates and passes a VC frame pulse indicating the head of the VC signal to a delay buffer part 22. A readout timing generation part 26 shifts the readout timing forward or backward by one byte of the VC signal when a write/read phase monitor part 28 makes a stack request for controlling a readout phase so as to increase a write and read phase difference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDH (Synchronous
ous Digital Hierarchy) The present invention relates to a non-instantaneous-interruption switching system that forms a transmission line redundant configuration of a digital transmission system, and a pointer termination unit used therein.

[0002]

2. Description of the Related Art Conventionally, a non-instantaneous power switching method in which a transmission side frame signal is duplicated and transmitted from a transmitting side and any one of them is selected at a receiving side, and is switched without an instantaneous interruption at the time of switching, is disclosed in -79208 (Patent 2,611,629)
No.). According to the publication, when the phase difference between the active system and the standby system is larger than the frame pulse width, the frame pulse matches. However, since switching is performed using different data, instantaneous interruption occurs and the phase difference within one frame is reduced. In this case, a multi-frame pulse is generated from the frame pulse extracted from the transmission path frame signal, and the data of both systems are compared and controlled for each frame within the multi-frame, so that both Even when the phase difference between the transmission line frame signals of the two systems is more than one frame, instantaneous interruption switching can be performed without using a variable delay means other than the elastic store. It is described that instantaneous interruption switching can be performed by detecting a phase difference.

[0003] Further, regarding a redundant system switching system of an SDH transmission system for transmitting a signal specified by a synchronous interface (NNI), Japanese Unexamined Patent Publication No. Hei 8-65262 (Japanese Patent No.
No. 669,355) is provided with a transmission line switching selection circuit for selecting one of the N lines and transmitting it to the protection transmission line on the transmission side, and having a management unit (AU) on the reception side of the protection transmission line. AU pointer value having the same frame phase as the output synchronous transfer (STM) frame phase of the switching circuit and having the same AU pointer value as the value of the AU pointer selected by the selection circuit for selecting one of the N pieces of AU pointer value information It is described that the switching from the active system to the standby system is instantaneously interrupted by adjusting the output phase of the signal by the delay circuit so that Also,
In an SDH synchronous transmission device recommended in CCITT, G707, 708, and 709, an NNI (Network Node Int) input from a transmission device via a different transmission path is used.
Japanese Patent Application Laid-Open No. 7-19 / 1994 relates to a transmission path signal switching method for switching a received transmission signal having a frame configuration without instantaneous interruption.
In Japanese Patent No. 3560 (Patent No. 2,771,440), the detection of a phase difference caused by a difference in the amount of delay of a received signal passing through two different transmission paths is performed by folding a marker transmitted from the transmission side at the opposite station, thereby detecting the absolute value of the transmission path. By measuring the delay time and simultaneously measuring the frame phase difference using the frame synchronization signal, finding the corrected delay difference from both, and matching it with the delay circuit, accurate and stable phase difference detection is possible and instantaneous interruption switching Is described.

[0004] Next, regarding the conventional hitless switching method,
This will be described with reference to FIG. FIG. 10 is a block diagram showing a known type of hitless switching method. Conventionally, this kind of instantaneous interruption switching system, as shown in FIG. 10, splits a transmission signal in a transmitting device, transmits the same signal to both transmission lines, This is applied to a transmission line switching system having a redundant configuration for selecting one of the signals received from the communication system.

[0005] As means for non-stop switching, the transmitting side transmits a multi-frame from the multi-frame generating section 401 to a vacant time slot of the transmitting signal before the branching section 403 for transmitting the same signal to both systems. A multi-frame pattern insertion unit 402 for inserting a frame pattern is provided. The receiving side performs multi-frame synchronization with multi-frame synchronization circuits 408 and 409 with respect to received signals from both transmission paths. In the control unit 410 having
The multi-frame phases of the received signals of both systems are compared to determine the relative delay difference at the receiving end.

[0006] Based on this delay difference, delay buffers 411,
The delay amount given at 412 is set, and the phases of the signals of both systems after passing through the delay buffer are matched. As a result, as shown in the time chart of FIG. 9, the delay difference between the two transmission paths can be eliminated at the receiving end (before the selection unit 413).
Therefore, when the signals of both systems are switched, it is possible to execute switching without data loss or duplication, that is, without instantaneous interruption.

FIGS. 10 and 9 show a configuration diagram and a time chart focusing only on signals from the station A to the station B. As shown in FIGS. 9 (c-1) to 9 (c-2), FIG. The phase of the 0-system shown in (c-3) is determined so as to match the synchronization frame, and the VC frame phase in which the readout counter is shifted forward according to the read-out phase difference is advanced to match the 0-system side, and The instantaneous interruption switching method has been achieved. On the other hand, in the case of having a bidirectional transmission path, the signal from the station B to the station A is similarly provided with the above-mentioned means necessary for the transmission side and the reception side, so that the bidirectional transmission between the A and B stations Instantaneous interruption switching in communication becomes possible.

[0008]

However, the conventional hitless switching system has the following problems.

The first problem is that the conventional instantaneous interruption switching system is
A multi-frame configuration is effective when the delay difference between the two transmission paths is one frame or more. In a system based on the assumption that a delay difference smaller than one frame is generated, the multi-frame Does not need to be configured, and there is a large useless portion in the configuration.

The second problem is that the conventional instantaneous interruption switching system is
When applied to the DH transmission apparatus, the transmission path terminating units 406 and 407 in FIG. 7 may have a pointer processing function. The pointer processing function originally transmits a main signal from the transmission path clock to the internal clock of the apparatus. ES for changing
Since it has a memory, the ES memory necessary for the pointer processing function and the memory for absorbing the delay difference of the instantaneous interruption switching are independently provided, and the use efficiency of the memory cannot be said to be effective.

An object of the present invention is to share an ES memory used for a pointer processing function and a memory for absorbing a delay difference of instantaneous interruption switching in an SDH transmission system, and synchronize the pointer processing of both systems with each other. It is another object of the present invention to provide means for realizing instantaneous interruption switching with a simpler hardware configuration by adding means.

[0012]

SUMMARY OF THE INVENTION The present invention relates to an SDH (Sync
hronous Digital Hierarchy) In a hitless switching system having a transmission line redundant configuration of a digital transmission system, pointer termination portions of a plurality of transmission lines of the transmission line redundant configuration are:
A pointer detection unit for detecting a pointer value from the transmission path, a frame header generation unit for generating a frame header based on the pointer value from the pointer detection unit, and a delay buffer for delaying data from the transmission path from the pointer detection unit , A pointer insertion unit that inserts a pointer into data read from the delay buffer unit, and a phase comparison that compares a VC frame phase received from a pointer termination unit of another system with a VC frame phase read from the delay buffer unit. And a read timing generation unit that stops reading only in a pulse output section based on a phase difference of the comparison result of the phase comparison unit, and the read timing generation unit stops reading in the pointer insertion unit only in the pulse output section. Thus, the read timing is shifted.

Further, the present invention relates to an SD having a redundant transmission path.
At the end of the pointer of each transmission line of an H (Synchronous Digital Hierarchy) digital transmission system, the S received from either the transmission line of the working system or the transmission line of the protection system.
A pointer detecting section for detecting pointer bytes (H1, H2 bytes) of the DH signal and extracting the pointer value; and a VC (Virtual Container) received from the pointer detecting section.
r) A delay buffer unit having an ES memory for writing a signal, a transmission line frame phase generated by a write timing generation unit for generating a timing for writing the VC signal to the delay buffer unit, and the pointer detection unit A frame header generation unit that finds the beginning of the VC signal from the received pointer value, generates a VC frame pulse indicating the beginning of the VC signal, and writes the generated VC frame pulse into the delay buffer unit; and the delay buffer unit based on a transmission line clock. A pointer insertion section that sequentially reads and passes a VC signal and a VC frame pulse that are periodically written to the ES memory based on the internal clock, and a phase of the VC frame pulse that is sequentially read based on the internal clock. A transmission port for calculating a phase difference from the in-device frame phase generated by the read timing generation unit. An inter calculation unit, a phase comparison unit that compares a VC frame phase received from a pointer termination unit of another system with a VC frame phase read from the delay buffer of the own system, and outputs the phase difference to a read timing generation unit; A read timing generator for shifting the read timing of the delay buffer by suspending the read only during the pulse output section when a phase difference pulse is received from the phase comparator; When there is a stuff request for controlling the read phase to separate the read phase difference, the read timing is shifted back and forth by one byte of the VC signal.

The present invention has a read timing section together with a write timing generation section of a delay buffer section, and reads a delay buffer to compare a VC frame phase with a VC frame phase received from a pointer termination section of another system. Therefore, the phase difference between the pointers of the selected transmission system and the selected transmission system can be matched, and the instantaneous interruption switching can be achieved by switching after the matching of the phase difference. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

First Embodiment (1) Description of Configuration First, the present invention will be described with reference to FIG. 1, in a redundant configuration of an SDH digital transmission system, between a working transmission line and a protection transmission line. When there is a delay difference between signals passing through both transmission lines due to a distance difference, the phase of both signals is matched by using a memory that absorbs the delay difference. The method will be described.

In the first embodiment of the present invention, when the distance difference between the two transmission paths is sufficiently smaller than one frame equivalent (about 25 km in distance conversion) (in the case of an intra-station transmission path, etc.), In AU (Administrative Unit) pointer processing for coupling a higher-order path layer to an section layer with respect to an SDH frame, the phases can be matched by synchronizing pointer processing of both systems.

In FIG. 1, a redundant path is formed from a transmission apparatus A having a transmission and reception unit, a transmission apparatus B having a transmission and reception unit, a short-distance working transmission path, and a short-distance protection transmission path. A transmission system having the same. The two transmission devices A and B respectively terminate the receiving-side branch units 103 and 104 for branching into the working system and the protection system, the transmission line terminating units 107 and 109 for terminating the working system transmission and reception unit, and the protection system transmission and reception unit. Transmission line termination units 108 and 119 to be used, an active transmission line,
And a spare transmission path. Also, transmission devices A and B
In each case, a network management device (not shown) performs the initial setting of the transmission line of the working system or the protection system, and manages the operational failure route and the failure state of the device, and issues a request for a route change when a failure occurs. It instructs the branching unit 103, the transmission path terminating unit 107, and the like.

FIG. 2 shows the configuration of the transmission line terminating unit of both end devices (transmission devices A and B in FIG. 1) for realizing the instantaneous interruption switching system according to the present invention based on the redundant configuration of FIG. ing. Pointer termination units 1 and 2 are ITU-T recommendations
Pointer processing shall be performed based on the provisions of G.783 AnnexA. The selection unit 3 is a selector for performing redundancy switching for a main signal having a pointer that has been replaced by the pointer termination units 1 and 2 based on a frame in the device.

The pointer terminating units 1 and 2 mutually exchange the VC frame phase of their own system via a signal line 4.
Further, in general, each of the pointer terminating units 1 and 2 has an E for changing from the transmission line clock to the internal clock.
It has an S memory, manages the write phase and read phase of the ES memory, and when the phases approach each other,
In order to perform control to shift the phase on the read side, a stuff request is generated as a read pointer, and stuff processing is performed on the payload.

In such stuff generation of the pointer termination units 1 and 2, a stuff request generated on its own side is exchanged with each other through a signal line 5.

Each of the pointer processing units 1 and 2 compares the VC frame phase of its own system with the VC frame phase of the other system, and if the own system side is more advanced, it sets the read phase of the ES memory to the phase. By shifting by the difference, an operation of matching with the VC frame phase of the other system is performed. As a result, the VC frame phases of both systems match.
Also, after the match, the pointer termination units of both systems monitor the stuff request 5 generated in the other system in addition to the stuff request generated in the own system. By generating a pointer and performing a stuff operation, even when a stuff request occurs in either system, it is possible to keep the VC frames in both systems consistent.

Therefore, the V voltages of both systems input to the selection unit
The C signal has exactly the same phase including the case where the stuff operation is performed. That is, when the signals of both systems are switched by the selection unit 3, the switching can be performed without data loss or duplication, that is, without instantaneous interruption.

The configuration of the hitless switching device in the SDH transmission system according to the first embodiment of the present invention will be described with reference to FIG. . FIG. 3 shows an example of a detailed configuration of the pointer termination units 1 and 2 shown in FIG.

In FIG. 2, pointers 1 and 2 are provided on both of the duplexed working transmission line and the protection transmission line, respectively. The signal transferred to the frame is sent to the selection unit 3. The selection unit 3 is a selector for switching between the two transmission lines that have been duplexed.

FIG. 3 is a block diagram of the pointer termination unit 1 and 2 shown in FIG.
2 shows a detailed configuration. The pointer detection unit 11
Pointer bytes (H1, H2 bytes) of the SDH signal received from either the working transmission line or the protection transmission line
Is detected, its value is extracted, and the frame header generation unit 1
Hand over to 5. The frame header generator 15 includes: a transmission line frame phase generated by the write timing generator 14;
From the pointer value received from the pointer detection unit 11, V
A C (Virtual Container: a device for storing information, composed of an information area and a maintenance operation POH) finds the head of the signal and generates a VC frame pulse indicating the head of the VC signal.

The delay buffer 12 includes a pointer detector 11
ES for writing the VC signal received from the controller and the VC frame pulse received from the frame header generator 15.
A memory that periodically writes them to the ES memory based on the transmission line clock. The VC signal and the VC frame pulse written in the delay buffer 12 are sequentially read out based on the internal clock and passed to the pointer insertion unit 13. At this time, the transmission pointer calculator 17 calculates the phase difference between the VC frame pulses read from the delay buffer 12 based on the in-device frame phase generated by the read timing generator 16.

The phase comparator 19 compares the VC frame phase received from the pointer termination unit of the other system with the delay buffer 1 of the own system.
2 is compared with the VC frame phase read out from the second and the phase difference is output to the readout timing generation unit 16. When receiving the phase difference pulse from the phase comparator 19, the read timing generator 16 shifts the read timing by stopping the read only during the pulse output section, and
When there is a stuff request from the read phase monitoring unit 18 to control the read phase to separate the write / read phase difference, the read timing is shifted back and forth by one byte of the VC signal. The write / read phase monitoring unit 18 compares the two based on the write phase and the read phase to the delay buffer 12 and transmits a stuff request to the transmission pointer calculation unit 17 when the phase difference between the two approaches each other. I do.

The transmission pointer calculation section 17 calculates a pointer value from the in-device frame pulse received from the read timing generation section 16 and the VC frame pulse read from the delay buffer 12, and sends it to the pointer insertion section 13. At this time, if there is a stuff request from the write / read phase monitoring unit 18 of the own system and the pointer end unit of the other system, a stuff operation and a pointer value indicating the stuff request are generated and then inserted. The pointer value to be transmitted is sent to the pointer insertion unit 13.

The pointer insertion unit 13 includes a delay buffer 12
The VC signal read from the
The received pointer value is added to the pointer byte and transmitted into the device.

(2) Description of Operation Next, the operation of the pointer termination units 1 and 2 in FIGS. 2, 3 and 4 will be described with reference to time charts shown in FIGS.

FIG. 4 shows an example of the configuration of a pointer termination unit for implementing general pointer processing. First, FIG.
The operation of general pointer processing (processing performed by the pointer termination units 1 and 2) will be described with reference to the time chart of FIG.

In FIG. 4, a pointer detecting section 21 detects pointer bytes (H1, H2 bytes) of an SDH signal received from one of a working transmission line and a protection transmission line, and extracts the value. , Frame header generation unit 15
Pass to The frame header generation unit 15 calculates a VC (Virtual Cont
ainer: Information area and PO for maintenance and operation in a container for storing information
H) and finds the beginning of the signal, generates a VC frame pulse indicating the beginning of the VC signal, and
Pass to.

The delay buffer 22 includes a pointer detector 21
For writing the VC signal received from the frame header generating section 25 and the VC signal received from the frame header generating section 25.
A memory that periodically writes them to the ES memory based on the transmission line clock. The VC signal and the VC frame pulse written in the delay buffer 22 are sequentially read out based on the internal clock and passed to the pointer insertion unit 23. At this time, the transmission pointer calculation unit 27 determines the VC read from the delay buffer unit 22 based on the in-device frame phase generated by the read timing generation unit 26.
Calculate the phase difference between frame pulses.

When there is a stuff request from the write / read phase monitoring unit 28 for controlling the read phase to separate the write / read phase difference, the read timing generation unit 26 sets the read timing to one byte of the VC signal. Perform the operation of shifting back and forth by minutes. The write / read phase monitoring unit 28 compares the two based on the write phase and the read phase to the delay buffer 22, and transmits a stuff request to the transmission pointer calculation unit 27 when the phase difference between the two approaches each other. I do.

The transmission pointer calculation unit 27 calculates a pointer value from the in-device frame pulse received from the read timing generation unit 26 and the VC frame pulse read from the delay buffer 22, and sends it to the pointer insertion unit 23. At this time, a pointer value to be inserted is sent from the write / read phase monitoring unit 28 to the pointer insertion unit 23.

The pointer insertion unit 23 includes a delay buffer 22
Is added to the VC signal read from the
The received pointer value is added to the pointer byte and transmitted into the device.

Next, this operation will be described with reference to the block diagram of FIG. 4 and the timing chart of FIG.
It is assumed that the phase of the transmission line frame input to is as shown in FIG. Therefore, the write timing generation unit 24
The transmission line frame pulse is generated with the phase of (a-2) (frame head position). The pointer detector 21 detects the pointer bytes (H1, H2 bytes) shown in (a-1) based on the transmission line frame pulse (a-2),
Retrieve the value. This pointer value indicates an offset value from the position of the pointer byte to the first byte where the VC frame is stored.

Using this pointer value, a VC frame pulse (a-3) indicating the beginning of the VC frame is generated.
VC signal (a-1) and VC frame pulse (a-3)
Are sequentially written to the delay buffer 22.

Next, V written in the delay buffer 22
The operation of adding a pointer value to the C signal and transmitting it to the apparatus will be described. The read timing generation unit 26 holds the in-device frame phase and outputs the in-device frame pulse (a-4). Here, the phase of the transmission line frame pulse (a-1) and the phase of the in-device frame pulse (a-4) are generally different (in the figure, the phases are shifted). From the frame pulse (a-4) in the device, pointer bytes (H1, H
(2 bytes) is determined, and counting up to the position of the VC frame pulse read from the delay buffer 22 is performed with reference to this position. The counted value becomes a pointer value to be added to the VC frame read from the delay buffer 22.

The pointer value to be added to this VC frame is passed to the pointer insertion unit 23,
Then, the pointer signal is inserted into the pointer byte position of the VC signal read from the delay buffer 22 as a pointer value and transmitted into the device.

In the pointer processing as described above, when the write phase to the delay buffer 22 and the read phase approach each other,
This is detected by the write / read phase monitoring unit 28. In this case, the pointer value added by the pointer insertion unit 23 inserts a value indicating a stuff request, and the delay buffer 2
It is necessary to perform a stuffing process on the VC signal read from the second and the write / read phase monitoring unit 28 issues an instruction for this to the transmission pointer calculation unit 27 and the read timing generation unit 26. .

The general pointer processing has been described above. In addition, the pointer value of the signal received from the transmission path is
(A) When the request is a positive stuff request, (b) When the request is a negative stuff request, (c) the operation when it is an NDF (New Data Flag), and (d) the alarm detection operation, In this case, there is no need to particularly explain, so the description is omitted.

Next, a pointer processing operation unique to the present invention will be described with reference to the time charts of FIGS. In the following, the transmission paths of each system in FIG. 2 are referred to as system 0 (working system) and system 1 (standby system), respectively.

First, in the 0-system pointer terminating unit 1,
In the VC frame pulse read from the delay buffer 12, the 1-system pointer terminating unit 2, the delay buffer 1
It is assumed that the VC frame pulses read out from No. 2 are respectively (b-1) and (b-2) in FIG. Here, the phase comparison unit 19 compares the phase of the VC frame pulse received from the other system with the phase of the VC frame pulse of the own system, and outputs the phase difference pulses of (b-3) and (b-5), respectively. Generated. In any case, the pulse generation method is performed from the VC frame pulse on the own system side to the VC frame pulse on the other system side.

Assuming that the phase difference between the two systems is sufficiently smaller than one frame, the allowable range of the phase difference is determined. By doing so, the readout phase determination pulse on the 0-system side becomes
It is determined that the value is smaller than the reference value, while the read phase determination pulse for the first system is determined to be larger than the reference value. Based on this result, the 0-system side, which was determined to be smaller than the reference value,
As the phase difference between the 0 system / 1 system, it is determined that “the own system is advanced”, and conversely, the 1 system side is determined that “the own system is late”. The phase comparison unit 19 of the 0-system side, which has determined that “the own system is advanced”, sets the 0-system reading stop pulse (b-4) as a pulse having a length corresponding to the phase difference.
Generate and output

The read timing generator 16 which has received this pulse stops reading from the delay buffer 12 by the length of this pulse, thereby delaying the read phase of the VC signal by the length of the pulse. As a result of such control of the readout phase, the readout phase of the next frame and subsequent frames match the readout phase of the VC frame of the other system.

On the other hand, the phase comparison unit 19 of the first system, which has determined that “the own system is behind”, does not generate the previous read stop pulse, so that the read phase control as in the zero system is not performed. The conventional readout phase is maintained. 0
By such an operation of the system / 1 system, the pointer values inserted by the pointer insertion units 13 of the respective systems have the same value, and the phases of the signals output from the pointer termination units 1 and 2 are in the same state.

In the second and subsequent frames in FIG. 6, the VC frame pulses of both systems match. Here, in each system,
When a stuff request is generated by the write / read phase monitoring unit 18, a stuff operation, that is, an operation of shifting the read phase, is performed. This operation is performed as in the general system described with reference to FIGS. If the operations are performed independently of each other, this operation causes a shift in the pointer values of both systems, and makes it impossible to maintain a state where the phases match.

In the present invention, the stuff request generated by the write / read phase monitoring unit 18 is also notified to the other systems. Therefore, each system performs stuff operation on both the own system and the other system stuff requests. It will be. Therefore, the staff operations of both systems are always performed simultaneously. In this way, even if a stuff request occurs in any one of the systems after the phases of the two systems have been once matched, the state in which the phases of both the systems match can be maintained.

[Second Embodiment] An instantaneous interruption switching system will be described as a second embodiment of the present invention. The basic configuration is as described in the first embodiment, but another method for matching the pointer values of both systems will be described.

FIG. 8 shows an example of the configuration. With respect to FIG.
A switching control unit 506 is added. The switching control unit 506 outputs a selection control signal 507 for the active / standby system to the selection unit 5.
03 and each of the pointer termination units 501 and 502 are notified.

The selection control signal 507 is a signal indicating “0 system” or “1 system”. For example, “0 system” indicates that the switching control unit 506 has instructed each unit to select the 0 system side. Show.

The difference from the previous embodiment lies in that the pointer terminating units 501 and 502 operate so that the non-selected system side matches the pointer value of the selected system side. Hereinafter, the operation will be described based on the time chart shown in FIG. The configuration of the pointer termination units 501 and 502 is almost the same as that of FIG. 3 described in the previous embodiment, but FIG. 8 shows a diagram including the control signal 507 from the switching control unit 506.

The control signal from the switching control unit 506 is drawn into the phase comparison unit 619 shown in FIG.

As an operation example, the switching control unit sets “0 system selection”.
The following describes an example of a case in which the instruction is given. The pointer termination unit 501 on the 0-system side recognizes that the own system is on the “selection-system” side in the phase comparison unit 619, and does not output a pulse to the read timing generation unit 616. Therefore, it operates in the same manner as general pointer processing. On the other hand, the pointer terminating unit 502 of the first system recognizes that the own system is the “non-selected system” in the phase comparing unit 619.

Here, the VC frame pulse on the self system side is shown in FIG.
With reference to (c-2), the VC frame pulse (c
The phase difference of -1) is measured, and a pulse (c-3) corresponding to the length of the phase difference is generated. Here, the local system VC
Since the frame pulse (c-2) is used as a reference, it is determined that "the other system is advanced by X bytes". If the other system is advanced, the read timing generation unit 61 of the own system
6, the readout phase corresponding to the phase difference (X bytes)
Shift to advance only. On the other hand, if the other system is delayed, the read phase in the read timing generation unit 616 of the own system is shifted so as to be delayed by the phase difference equivalent (X bytes).

If the phases match, no control is performed. In this way, the non-selected system 1 operates so as to match the pointer value of the selected system 1 with the pointer value, so that the pointer values of the two systems are the same as in the previous embodiment. Are matched.

[0059]

As described above, the present invention has the following effects.

The first effect is that the ES memory of the delay buffer unit for the pointer processing and the ES memory for the instantaneous interruption switching are shared, so that the instantaneous interruption switching function of the working system and the standby system is provided. That is, it is realized with a smaller hardware configuration.

The second effect is that, similarly, since a multi-frame is not formed unlike the conventional method, a simple hardware configuration suitable for a case where the delay difference between the two transmission paths is sufficiently smaller than one frame. It can be realized by.

The third effect is that, when the pointer processing and the phase matching processing are shared, the stuff request generated in the pointer processing is exchanged between the two systems, so that even after the stuff request generated after the phase matching is generated. That is, it is possible to maintain a phase-matched state and realize a highly reliable instantaneous interruption switching function.

[Brief description of the drawings]

FIG. 1 is a conceptual system diagram of a hitless switching system according to an embodiment of the present invention.

FIG. 2 is a part of a conceptual system diagram of a hitless switching method according to an embodiment of the present invention.

FIG. 3 is a block diagram of a pointer termination unit of a hitless switching method according to an embodiment of the present invention.

FIG. 4 is a block diagram of a general pointer termination unit of a hitless switching method according to an embodiment of the present invention.

FIG. 5 is a timing chart of a general pointer termination unit of the hitless switching method according to the embodiment of the present invention.

FIG. 6 is a timing chart of a pointer termination unit of a hitless switching method according to an embodiment of the present invention.

FIG. 7 is a part of a conceptual system diagram of an instantaneous interruption switching system according to an embodiment of the present invention.

FIG. 8 is a block diagram of a pointer termination unit of an instantaneous interruption switching system according to an embodiment of the present invention.

FIG. 9 is a timing chart of a conceptual system diagram of a hitless switching method according to an embodiment of the present invention and a conventional example.

FIG. 10 is a conceptual system diagram of a conventional example of a hitless switching method.

[Explanation of symbols]

 1, 2, 501, 502 Pointer termination unit 3, 503 selection unit 4 Communication path with other system pointer termination unit 5 Communication path with other system pointer termination unit 11, 21, 611 Pointer detection unit 12, 22, 612 selection buffer Units 13, 23, 613 Pointer insertion unit 14, 24, 614 Write timing generation unit 15, 25, 615 Frame header generation unit 16, 26, 616 Read timing generation unit 17, 27, 617 Transmission pointer calculation unit 18, 28, 618 Write / read phase monitoring unit 19, 619 phase comparison unit 101 transmission device A 102 transmission device B 103, 104 branch unit 105, 106 selection unit 107, 108, 109, 110 transmission line termination unit 401 multi-frame generation circuit 402 multi Frame insertion unit 403 Branch unit 404, 405, 406, 407 Transmission line termination unit 408, 4 09 Multi-frame synchronization circuit 410 Control unit 411, 412 Delay buffer unit 413 Selection unit 505 Switching control unit

Claims (7)

[Claims] 1. An SDH (Synchronous Digital Hierarch)
y) In the hitless switching method having a transmission line redundant configuration of the digital transmission system, the pointer termination units of the plurality of transmission lines of the transmission line redundant configuration include a pointer detection unit that detects a pointer value from the transmission line, A frame header generator for generating a frame header based on the pointer value from the pointer detector, a delay buffer for delaying data from the transmission path from the pointer detector, and data read from the delay buffer A pointer insertion unit that inserts a pointer into a pointer, a phase comparison unit that compares a VC frame phase received from a pointer termination unit of another system with a VC frame phase read from the delay buffer unit, and a comparison result of the phase comparison unit. A read timing generator for stopping reading only during a pulse output section due to a phase difference, The generating unit instantaneous switching system, characterized by shifting the read timing by stopping the reading on the pointer insertion section only the pulse output interval. 2. The non-instantaneous interruption switching method according to claim 1, wherein the phase comparison unit notifies each other of the frame processing between both of the pointer processings of the two systems that are mutually switched in the transmission line redundant configuration. The non-instantaneous interruption switching method is characterized in that the pointer values of both systems are set to the same value, and the phases are matched at the preceding stage of the selector for redundant system switching. 3. The non-instantaneous interruption switching system according to claim 1, wherein the stuff generated in the mutual pointer processing after mutual phase matching between both of the pointer processing of the two systems which are mutually switched in the transmission line redundant configuration. A non-instantaneous-interruption switching method characterized in that by mutually notifying the requests, the pointer values of the two systems are maintained at the same value, and the phases are matched at the preceding stage of the redundant system switching selector. 4. The non-instantaneous interruption switching system according to claim 1, further comprising: a switching control unit for instructing switching of a transmission line, in addition to pointer termination units of the plurality of transmission lines in the transmission line redundant configuration. The selection information is notified to the phase comparator of the pointer termination unit, the pointer termination unit for performing phase matching with reference to another system is designated, and the output of the pointer termination unit and the output of the pointer termination unit of the other system are switched. Non-instantaneous interruption switching method. 5. An SDH (Synchronou) having a redundant transmission path.
s Digital Hierarchy) Pointer bytes (H1, H2 bytes) of the SDH signal received from either the working transmission line or the protection transmission line at the pointer end of each transmission line of the digital transmission system.
And a VC (Virtual Co.) received from the pointer detector.
ntainer) A delay buffer unit having an ES memory for writing a signal, a transmission line frame phase generated by a write timing generation unit for generating a timing for writing the VC signal to the delay buffer unit, and the pointer detection unit. A frame header generating unit that finds the head of the VC signal from the received pointer value, generates a VC frame pulse indicating the head of the VC signal, and writes the generated VC frame pulse in the delay buffer unit; Signal and VC periodically written to the ES memory
A pointer insertion unit for sequentially reading and passing frame pulses based on the internal clock; a phase of the VC frame pulse sequentially read based on the internal clock; and an internal frame phase generated by the read timing generation unit A transmission pointer calculation unit for calculating a phase difference between the VC frame phase and the VC frame phase received from the pointer termination unit of the other system and the VC frame phase read from the delay buffer of the own system; A phase comparator for outputting the phase difference pulse, and a read timing generator for shifting the read timing of the delay buffer unit by stopping reading only for a pulse output section when a phase difference pulse is received from the phase comparator. -There was a stuff request to control the read phase in order to separate the write / read phase difference by the read phase monitor. Pointer terminating unit and performs an operation for shifting the read timings in case the front and rear by VC signal 1 byte. 6. The pointer termination unit according to claim 5, wherein said write / read phase monitoring unit comprises:
A pointer termination unit that compares the two based on a write phase and a read phase for a unit, and transmits a stuff request to the transmission pointer calculation unit when the phase difference approaches each other. 7. The pointer termination unit according to claim 5, wherein the transmission pointer calculation unit calculates a pointer value from an internal frame pulse received from the read timing generation unit and a VC frame pulse read from the delay buffer. And sends it to the pointer insertion unit, and generates a stuff operation and a pointer value indicating a stuff request when there is a stuff request from the write / read phase monitoring unit and the other system pointer termination unit of the own system. And transmitting the pointer value to be inserted to the pointer insertion unit after performing the above operation.