JP2868398B2 - Transmission line switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for digital communication. The present invention relates to duplex transmission paths. INDUSTRIAL APPLICABILITY The present invention is used as a device for switching a digital signal arriving via two different transmission paths in accordance with the delay. The present invention is suitable for use in a power digital communication network.

[0002]

2. Description of the Related Art In order to improve reliability, a transmission line is configured as a network, and a system is automatically switched so that communication is not interrupted even if a signal is interrupted due to a failure or maintenance work on one transmission line. Is planned. As a conventional transmission line switching device for this purpose, there is a technique described in Japanese Patent Application Laid-Open No. 63-98259. In this conventional device, signals arriving via two different transmission paths are temporarily stored in a delay compensation memory, respectively, the delay compensation amount of the memory is adjusted, the frame phase is matched, and switching is performed. Is what you do.

[0003]

The prior art device can be used for a duplicated transmission line passing through substantially the same route, for example, for switching between the active and standby systems, but via a transmission line having a network configuration as described above. It is not suitable for switching between the two signals. In other words, a network-configured transmission path normally receives signals via the shortest distance route, but if for some reason it becomes impossible to receive signals via that route, it will be extremely remote. It may be necessary to switch to a signal of a route that bypasses. In that case, the phase difference between the two signals exceeds the range of the frame, and the above-described conventional apparatus cannot be used as it is.

In the prior art, the timing of the first bit of the frame is compared by synchronizing the frames. Therefore, if the standard frame length is 125 μS, the half of the standard frame length is ± 62.5 μS. It is effective for time shifts in the range, but does not work effectively for time shifts beyond that. The above ± 62.5 μS is approximately 20 km with respect to the propagation speed of light, but the difference between the distances of the two routes can often reach several hundred km in a network-structured transmission line. Can not do.

[0005] More specifically, with respect to a transmission line having an NNI frame structure, a technique for switching a conventional device will be described with reference to the drawings.

FIG. 3 is a diagram showing the overall configuration of a digital transmission line using an NNI frame signal.

[0007] In the first section termination generator 13 which receives the VC-3 and four paths generated by the first VC path termination generator 12, the output NNI frame signal is branched into two, and the same signal is output. Are output to both the first transmission line 10 and the second transmission line 11, respectively. After each of the NNI frame signals input to the second section end generating device 14 from the first transmission line 10 and the second transmission line 11 via different paths, after one of them is selected, the second VC path It is sent to the termination generation device 15.

Here, the processing of the signal having the NNI frame input from the transmitting device to the second section end generating device 14 through the two different first transmission lines 10 and the second transmission line 11 and the switching method thereof are described. explain.

FIG. 4 is a block diagram showing a configuration of a receiving unit of the switching device for generating section end. After the SOH (section overhead) of the NNI frame is terminated in the first and second receiving interface units 1 and 2, the AU pointer value changing process accompanying the transfer from the transmission line clock to the internal clock is performed. , VC-
3, VC-4 is output. Each VC- output from the first and second receiving interface units 1 and 2
3, VC-4 is input to the selector 8, the selector 8 is switched by external control, and the switching from the first transmission line 10 to the second transmission line 11 or the second transmission line 1
Switching from 1 to the first transmission path 10 is performed.

As described above, in the conventional transmission line switching system, when an NNI frame signal is input via two different paths, the delay amount differs if there is a path difference between the signals. When pointer processing is involved in the device that performs the processing, the pointer value is different, so the VC position in the NNI frame is different. Therefore, when switching signals by switching the selector under external control, the signal phase of the switching source and the signal of the switching destination do not match, and there is a problem that signal discontinuity occurs at the time of switching and instantaneous interruption occurs. there were.

The present invention has been made in view of such a background, and an object of the present invention is to provide a method capable of instantaneously switching a transmission path for a signal having a phase difference over a plurality of frames. I do. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for switching a transmission line arranged on a transmission line configured in a network.

[0012]

This onset Akira [Summary of] is, CCITT standard G707 arriving via two different transmission paths, the
NNI frame specified in any of 708 and 709
Two reception interface units for receiving a signal having a configuration, two delay memories for temporarily storing the outputs of the reception interface units, a selector for selecting one of the readout outputs of the two delay memories, and the two A control circuit for controlling the delay amounts of the two delay memories so that the phases of the read outputs of the delay memories coincide with each other, wherein the two delay memories have a capacity corresponding to a plurality of frames of the signal. Have this multiple frame
Is the H4 byte of the NNI frame . For signals having different phases over a plurality of frames of the output signals of the two receiving interface units, the synchronization timing is based on the pointer of the H4 byte of the NNI frame inserted on the transmitting side of the signal. And a synchronizing circuit for detecting and providing the control signal to the control circuit.

[0013]

According to the method of the present invention, a predetermined pointer is inserted on the transmitting side in a time span of a plurality of frames. On the receiving side, the ponita is detected, and a time difference over a plurality of frames is appropriately detected.

More specifically, the signal on the transmission path is CCI
When the signal has the NNI frame configuration defined in any of the TT standards G707, 708, and 709, N
The time difference is detected using the pointer inserted for the H4 byte of the NI frame. Thereby, 125 μS × 48 (frames) / 2 = 3 ms, that is, non-instantaneous switching can be realized even for a signal having a time difference of ± 3 mS.

Thus, when the transmission path is configured as a network, it is possible to sufficiently realize instantaneous interruption switching even for signals arriving via different paths.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

The transmission line switching apparatus 101 of the present invention comprises a first interface unit 1 and a second reception interface unit 2 for receiving signals arriving via two different transmission lines, A first delay memory 5 and a second delay memory 6 for temporarily storing outputs of the interface unit 1 and the second reception interface unit 2, respectively;
The selector 8 for selecting one of the read outputs of the first delay memory 5 and the second delay memory 6 and the selector 8 so that the phases of the read outputs of the first delay memory 5 and the second delay memory 6 match. A control circuit 7 for controlling the amount of delay,
Further, as a feature of the present invention, the first delay memory 5 and the second delay memory 6 have a capacity corresponding to a plurality of frames of the signal, and the outputs of the first reception interface unit 1 and the second interface unit 2 are output. A first synchronizing circuit 3 and a second synchronizing circuit 4 are provided for detecting a synchronization timing of a signal having a different phase over a plurality of frames of the signal on the basis of a pointer inserted on the transmission side of the signal and providing the detected synchronization timing to a control circuit 7.

The signal arriving via the transmission path is C
This is a signal having an NNI frame configuration defined in any of the CITT standards G707, 708, and 709, and the plurality of frames are H4 bytes of the NNI frame.

The transmission line switching device 10 configured as described above
As an example of the transmission path switching method using the C.I., as shown in FIG. 2, a transmission device 200 that inserts at least one identifiable pointer for a plurality of frames and transmits a signal when generating a frame signal, There is a receiving apparatus 100 that receives a signal via two different transmission paths, and the receiving apparatus 100 includes a transmission path switching apparatus 101.

Next, the operation of the embodiment of the present invention configured as described above will be described.

The N input from the first transmission line 10 and the second transmission line 11 from the transmitting device 200 via different paths
The signal having the NI frame is sent to the first interface unit 1 and the second interface unit 2 by the NNI.
The SOH (section overhead) of the frame is terminated, and the pointer value for the intra-station frame phase is changed with the transfer from the transmission line clock to the intra-station clock.

In general, when an NNI signal is input via two different paths, if the signal has a line length difference, the amount of delay is different, so that the frame phase is different and the passing device involves pointer processing. If the pointer values are different,
Since the VC positions in the NNI frame are different, the phases of the VC-3 or VC-4 path signals output from the two systems of the first reception interface unit 1 and the second reception interface unit 2 do not match.

Therefore, the first VC path termination generating device 12 of the transmitting device 200 shown in FIG.
For example, 48 multiframes are configured in the H4 byte which is the POH of the VC-3 or VC-4 of the NI frame. The first synchronizing circuit 3 and the second synchronizing circuit 4 connected to the outputs of the first receiving interface unit 1 and the second receiving interface unit 2 shown in FIG. 1 detect the above-mentioned H4 byte multi-frame phase. Then, the multi-frame synchronization is established, and the received data is written into the first delay memory 5 and the second delay memory 6 each having a capacity corresponding to a maximum of 48 multi-frame lengths.

When reading from the first delay memory 5 and the second delay memory 6, when the phase of the switching destination is advanced, the delay amount of the switching destination is increased by the control circuit 7, and the delay amount of the switching destination is increased. If the phase is late,
By reducing the delay at the switching destination, control is performed such that the readout phases of the two signals are the same, and the phases of the signals arriving from the first transmission line 10 and the second transmission line 11 are matched to the selector 8. input. Since the signals input to the selector 8 have the same phase, when the selector 8 is switched by an external control, the transmission path is switched without instantaneous interruption without data discontinuity or duplication. Can be.

[0025]

As described above, according to the present invention, N
By constructing a multi-frame with the H4 byte data of the NI frame signal, the phase difference resulting from the difference in the delay amount of the signal passing through two different transmission paths is absorbed, and the instantaneous interruption without affecting the line service. Thus, there is an effect that the transmission path can be switched.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a transmission line switching system according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a transmission method of an NNI frame signal.

FIG. 4 is a block diagram showing a configuration on a receiving side of a transmission line switching device in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st receiving interface unit 2 2nd receiving interface unit 3 1st synchronous circuit 4 2nd synchronous circuit 5 1st delay memory 6 2nd delay memory 7 control circuit 8 selector 9 intra-station transmission interface unit 10th One transmission line 11 Second transmission line 12 First VC path end generation device 13 First section end generation device 14 Second section end generation device 15 Second VC path end generation device 100 Receiving device 101 Transmission line Switching device 200 Transmission device

Claims (1)

(57) [Claims] 1. Arriving via two different transmission paths
Any of CCITT standards G707, 708 and 709
Two receiving interface units for receiving a signal having the NNI frame structure defined in the above, two delay memories for temporarily storing the outputs of the receiving interface units, and one of the readout outputs of the two delay memories. A transmission line switching device comprising: a selector and a control circuit that controls a delay amount of the two delay memories so that phases of readout outputs of the two delay memories coincide with each other. It has a capacity corresponding to a plurality of frames, and the plurality of frames are H4 bytes of an NNI frame.
Ri, the phase different signal over a plurality of frames of the two receiving interface portion of the output signal, detects a synchronization timing H4 byte relative to Po <br/> interface of said NNI frames inserted on the transmission side of the signal A transmission circuit switching device provided with a synchronization circuit provided to the control circuit.