JPH01264427A - System for switching transmission line - Google Patents

System for switching transmission line

Info

Publication number
JPH01264427A
JPH01264427A JP9286588A JP9286588A JPH01264427A JP H01264427 A JPH01264427 A JP H01264427A JP 9286588 A JP9286588 A JP 9286588A JP 9286588 A JP9286588 A JP 9286588A JP H01264427 A JPH01264427 A JP H01264427A
Authority
JP
Japan
Prior art keywords
transmission line
information
delay
frame
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9286588A
Other languages
Japanese (ja)
Inventor
Hideo Tatsuno
秀雄 龍野
Ikuo Tokizawa
鴇沢 郁男
Nobuyuki Tokura
戸倉 信之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9286588A priority Critical patent/JPH01264427A/en
Publication of JPH01264427A publication Critical patent/JPH01264427A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To prevent the hit of a transmission line when the line is switched by transmitting the same information to currently used transmission lines and a standby transmission line and shifting frame phases so that they can be synchronized to each other, and bits in the frames can be made the same in value, then, completely synchronizing the information string which can be made to the one to be switched on both transmission lines. CONSTITUTION:At a transmitting side device 1 of a transmission line switching system the information string of the currently used transmission lines 2a-2d are branched by means of a transmission line changeover switch 11 and transmitted in parallel to a standby transmission line 3. The information strings from the transmission lines 2a-2d and 3 are received by the interface circuit 14 of a receiving side device 4 and the frame phase of the information string received from the lines 2a-2d is synchronized to that of the information string received from the line 3 by a frame synchronizing means including an elastic store memory 20. Then the two information strings outputted by the frame synchronizing means are compared with each other through a changeover switch 24, variable delay circuit 25, variable delay memory 33, etc., and the difference in delay between the information strings is measured in the unit of frames. The measured difference in delay is used for correcting the delaying quantities of the transmission lines 2a-2d.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は時分割多重ディジタル伝送に利用する。[Detailed description of the invention] [Industrial application field] The present invention is utilized for time division multiplexed digital transmission.

特に、現用の伝送路と予備用の伝送路とを切り替える伝
送路切替方式に関する。本発明は光フアイバ通信装置に
利用するに適する。
In particular, the present invention relates to a transmission line switching method for switching between a working transmission line and a backup transmission line. The present invention is suitable for use in optical fiber communication equipment.

〔従来の技術〕[Conventional technology]

第4図は従来例ディジタル伝送装置のブロック構成図で
ある。
FIG. 4 is a block diagram of a conventional digital transmission device.

送信側装置1では、多重化変換装置10によりディジタ
ル情報列をフレーム多重化し、伝送路切替スイッチ11
およびインタフェース回路12を介して現用伝送路2に
送出する。
In the transmitting side device 1, the digital information string is frame multiplexed by the multiplexing conversion device 10, and the transmission path changeover switch 11
Then, it is sent to the current transmission line 2 via the interface circuit 12.

受信側装置4では、現用伝送路2の信号をインタフェー
ス回路14で受は取り、伝送路切替スイッチ36を介し
て多重分離装置38に供給する。多重分離装置38は、
多重化された情報列を分離する。
In the receiving side device 4, the signal on the current transmission line 2 is received by the interface circuit 14, and is supplied to the multiplexing/demultiplexing device 38 via the transmission line changeover switch 36. The demultiplexer 38 is
Separate multiplexed information strings.

現用伝送路2において線路や伝送装置が故障した場合、
保守のために動作を停止させる必要がある場合、故障箇
所を修理した後に切り戻す場合等には、伝送路切替スイ
ッチ11および36により、現用伝送路2を予備用伝送
路3に切り替える。
If the line or transmission equipment breaks down in the current transmission line 2,
When it is necessary to stop the operation for maintenance or when switching back after repairing a faulty part, the transmission line changeover switches 11 and 36 are used to switch the working transmission line 2 to the backup transmission line 3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、従来の伝送路切替方式では、現用伝送路2から
予備用伝送路の切替を主信号とは無関係に行っていた。
However, in the conventional transmission line switching system, switching from the working transmission line 2 to the backup transmission line was performed regardless of the main signal.

このため、現用伝送路2と予備用伝送路3との間の遅延
差を吸収することができず、切替時に瞬断が生じ、主信
号の欠落や重複その他により同期がはずれ、正常な伝送
状態を維持できなくなる欠点があった。特に、高速の光
フアイバ通信装置では、現用伝送路と予備用伝送路との
間にフレーム長以上の伝搬時間差があり、現用予備の切
替でフレームの脱落または重複が発生する可能性がある
。これは実質的に伝送路の瞬断となる。
As a result, it is not possible to absorb the delay difference between the working transmission line 2 and the protection transmission line 3, causing instantaneous interruptions during switching, and loss of synchronization due to missing or duplicating main signals, resulting in normal transmission status. There was a drawback that it could not be maintained. In particular, in high-speed optical fiber communication devices, there is a propagation time difference greater than the frame length between the working transmission line and the protection transmission line, and there is a possibility that frames may be dropped or duplicated when switching between the working and protection transmission lines. This essentially results in a momentary interruption of the transmission path.

例えば数百Mb/s以上の基幹伝送路では、伝送路切替
時に非常に短時間の瞬断があっただけでも、下吹群の装
置および端末のすべてに大きく影響し、伝送品質が劣化
する欠点がある。
For example, in a backbone transmission line of several hundred Mb/s or more, even a very short momentary interruption when switching the transmission line has a major effect on all equipment and terminals in the Shimofuki group, resulting in deterioration of transmission quality. There is.

本発明は、以上の問題点を解決し、伝送路切替時の瞬断
をなくし、常に正常な伝送状態を維持できる伝送路切替
方式を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a transmission line switching method that solves the above problems, eliminates instantaneous interruptions when switching transmission lines, and can always maintain a normal transmission state.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の伝送路切替方式は、送信側装置に、現用伝送路
の情報列を分岐して予備用伝送路に並列伝送させる手段
を備え、受信側装置に、予備用伝送路から受信した情報
列のフレーム位相を現用伝送路から受信した情報列のフ
レーム位相に同期させるエラスティックストアメモリを
含むフレーム同期手段と、このフレーム同期手段の出力
する二つの情報列の内容を比較し、これらの情報列の遅
延差をフレーム単位で測定する手段と、この遅延差によ
り予備用伝送路の遅延量を補正する手段とを備え、送信
側装置と受信側装置との双方に、補正する手段による補
正の後に現用伝送路を切り離す手段を備えたことを特徴
とする。
In the transmission line switching system of the present invention, the transmitting side device is provided with means for branching the information string of the working transmission path and transmitting it in parallel to the protection transmission path, and the receiving side device is provided with a means for branching the information string of the working transmission path and transmitting it in parallel to the protection transmission path. A frame synchronization means including an elastic store memory that synchronizes the frame phase of the information string with the frame phase of the information string received from the current transmission path compares the contents of the two information strings output from this frame synchronization means, and a means for correcting the delay amount of the backup transmission line using this delay difference, and a means for correcting the delay amount of the backup transmission line based on the delay difference, and a means for measuring the delay difference of It is characterized by having a means for disconnecting the currently used transmission line.

遅延差を測定する手段は、二つの情報列のすべてのビッ
トを比較する必要はなく、−以上任意個のビットを比較
する。
The means for measuring the delay difference does not need to compare all the bits of the two information strings, but compares an arbitrary number of bits greater than or equal to -.

〔作 用〕[For production]

現用伝送路と予備用伝送路とに同一の情報を伝送させ、
そのフレーム位相を同期させる。その後に、そのフレー
ム内のビットが同じ値となるようにフレーム位相をずら
し、切替対象となる情報列を双方の伝送路で完全に同期
させる。さらに、完全に同期した状態で現用伝送路から
予備用伝送路を切り替える。これにより、伝送路切替時
の瞬断をなくすことができる。
The same information is transmitted on the working transmission line and the backup transmission line,
Synchronize the frame phases. Thereafter, the frame phase is shifted so that the bits within the frame have the same value, and the information strings to be switched are completely synchronized on both transmission paths. Furthermore, the protection transmission line is switched from the working transmission line in a completely synchronized state. This makes it possible to eliminate instantaneous interruptions when switching transmission paths.

〔実施例〕〔Example〕

第1図は本発明実施例ディジタル伝送装置のブロック構
成図である。この実施例は、光フアイバ伝送路を用いた
フレーム多重伝送装置に本発明を史施したものである。
FIG. 1 is a block diagram of a digital transmission device according to an embodiment of the present invention. In this embodiment, the present invention is applied to a frame multiplex transmission apparatus using an optical fiber transmission line.

この装置は、それぞれ一定長のフレームを単位として情
報列を伝送する現用伝送路2a〜2dおよび予備用伝送
路3を切り替えるため、送信側装置1に、現用伝送路2
a〜2dのいずれか、例えば現用伝送路2dの情報列を
分岐して予備用伝送路3に並列伝送させる伝送路切替ス
イッチ11を備え、受信側装置4に、予備用伝送路3か
ら受信した情報列のフレーム位相を現用伝送路から受信
した情報列のフレーム位相に同期させるフレーム同期手
段、すなわちインタフェース回路14、フレーム同期回
路17、エラスティックストアメモリ20および局クロ
ック源21と、エラスティックストアメモリ20の出力
する二つの情報列の内容を比較し、これらの情報列の遅
延差をフレーム単位で測定する手段、すなわち可変遅延
回路25、排他的論理和回路27、制御回路30と、こ
の遅延差により予備用伝送路3の遅延量を補正する可変
遅延メモリ33とを備え、送信側装置1と受信側装置4
との双方に、可変遅延メモリ33による補正の後に現用
伝送路を切り離す手段、すなわち送信側装置1に配置さ
れた伝送路切替スイッチ11および制御回路13と、受
信側装置4に配置された制御回路30.32および伝送
路切替スイッチ36と、制御回路13と制御回路32と
を接続するデータリンク39を備える。
In this device, in order to switch between the working transmission lines 2a to 2d and the protection transmission line 3, which transmit information sequences in units of frames of a fixed length, the transmitting side device 1 is configured to
A to 2d, for example, a transmission line changeover switch 11 that branches the information string of the working transmission line 2d and transmits it in parallel to the protection transmission line 3, and the receiving side device 4 receives information from the protection transmission line 3. Frame synchronization means for synchronizing the frame phase of the information sequence with the frame phase of the information sequence received from the current transmission line, that is, the interface circuit 14, the frame synchronization circuit 17, the elastic store memory 20, the station clock source 21, and the elastic store memory. means for comparing the contents of two information streams outputted by 20 and measuring the delay difference between these information streams on a frame-by-frame basis, that is, a variable delay circuit 25, an exclusive OR circuit 27, a control circuit 30, and this delay difference. A variable delay memory 33 for correcting the delay amount of the backup transmission line 3 is provided, and the transmission side device 1 and the reception side device 4
and a means for disconnecting the current transmission line after correction by the variable delay memory 33, that is, a transmission line changeover switch 11 and a control circuit 13 disposed in the transmitting side device 1, and a control circuit disposed in the receiving side device 4. 30, 32, a transmission line changeover switch 36, and a data link 39 that connects the control circuit 13 and the control circuit 32.

送信側装置1にはさらに、多重化変換装置10と、現用
伝送路2a〜2dおよび予備用伝送路3のそれぞれに対
応して設けられたインタフェース回路12とを備える。
The transmitting side device 1 further includes a multiplexing conversion device 10 and an interface circuit 12 provided corresponding to each of the working transmission lines 2a to 2d and the protection transmission line 3.

受信側装置4にはさらに、多重分離回路38を備える。The receiving device 4 further includes a demultiplexing circuit 38 .

この実施例では、任意の現用伝送路2a〜2dから予備
用伝送路3に、また、使用されていない現用伝送路があ
る場合にはその伝送路を予備伝送路として、他の伝送路
から無瞬断で切り替えることができる。この選択は、制
御回路30からの制御信号31により、切替スイッチ2
4を操作することにより行われる。
In this embodiment, any working transmission line 2a to 2d is connected to the protection transmission line 3, and if there is an unused working transmission line, that transmission line is used as a protection transmission line and is disconnected from other transmission lines. You can switch at a moment's notice. This selection is made by the control signal 31 from the control circuit 30.
This is done by operating 4.

ここで、現用伝送路2dを予備用伝送路3に切り替える
場合を例に、この装置の動作を説明する。
Here, the operation of this device will be described using a case where the working transmission line 2d is switched to the protection transmission line 3 as an example.

多重化変換装置10は、フレームパターンが挿入された
フレーム多重信号を伝送路切替スイッチ11に出力する
。伝送路切替スイッチ11は、制御回路13の制御によ
り、現用伝送路2dと予備用伝送路3とを並列に接続し
、現用伝送路2dの情報列を予備用伝送路に分岐する。
The multiplex conversion device 10 outputs the frame multiplexed signal into which the frame pattern has been inserted to the transmission path changeover switch 11. The transmission line selector switch 11 connects the working transmission line 2d and the protection transmission line 3 in parallel under the control of the control circuit 13, and branches the information string of the working transmission line 2d to the protection transmission line.

インタフェース回路12は、電気信号を光信号に変換し
て各伝送路に送出する。
The interface circuit 12 converts electrical signals into optical signals and sends them to each transmission path.

インタフェース回路14は、各伝送路毎に光信号を電気
信号に変換し、ビット同期をとってクロック15d 、
 16を再生する。フレーム同期回路17は、インタフ
ェース回路14の受信した情報列およびクロック15d
 、 16ヲ用いて、それぞれフレームパルス18d 
、 19を再生する。エラスティックストアメモリ20
は、フレームパルス18(! 、 19の位相を基準と
して、クロック15d 、 16によりそれぞれ受信情
報列を記憶する。エラスティックストアメモリ20の記
憶情報は、局クロック源21から供給される局フレーム
パルス230位相を基準として、同じく局クロック源2
1から供給される局クロック22により読み出される。
The interface circuit 14 converts the optical signal into an electrical signal for each transmission path, synchronizes the bits, and outputs a clock 15d,
Play 16. The frame synchronization circuit 17 receives the information string received by the interface circuit 14 and the clock 15d.
, 16 and each frame pulse 18d
, play 19. elastic store memory 20
stores received information sequences using clocks 15d and 16, respectively, with the phase of frame pulses 18 (!, 19 as a reference).The information stored in the elastic store memory 20 is based on the station frame pulse 230 supplied from the station clock source 21. Similarly, based on the phase, the station clock source 2
It is read out by the station clock 22 supplied from 1.

これにより、現用伝送路2dと予備用伝送路3との間の
受信情報列のフレーム位相が一致する。
As a result, the frame phases of the received information sequences between the working transmission line 2d and the protection transmission line 3 match.

切替スイッチ24は、制御回路30からの制御信号31
により、現用伝送路2dと予備用伝送路3との受信情報
列のみを可変遅延回路25に引込むように接続される。
The changeover switch 24 receives a control signal 31 from the control circuit 30.
As a result, only the received information sequences of the working transmission line 2d and the protection transmission line 3 are connected to the variable delay circuit 25.

この可変遅延回路25の出力は排他的論理和回路27に
供給される。制御回路30は、排他的論理和回路27の
出力を参照しながら、制御信号28.29により可変遅
延回路25の遅延量を変化させ、排他的論理和回路27
の出力が常時「0」になるように制御する。
The output of this variable delay circuit 25 is supplied to an exclusive OR circuit 27. The control circuit 30 changes the delay amount of the variable delay circuit 25 using control signals 28 and 29 while referring to the output of the exclusive OR circuit 27.
control so that the output is always "0".

すなわち、一方の可変遅延回路25の遅延量を最低とし
、他方の可変遅延回路25の遅延量をフレーム単位で増
加させて、排他的論理和回路27の入力が常時同一ビッ
ト符号となるように、すなわち排他的論理和回路27の
出力が常時「0」となるように制御する。上記他方の可
変遅延回路25の遅延量が最大となっても、排他的論理
和回路27の出力が常時「0」とならない場合には、上
記他方の可変遅延回路25の遅延量を最小とし、上記一
方の可変遅延回路25の遅延量を同様に増加させる。
That is, the delay amount of one variable delay circuit 25 is set to the minimum, and the delay amount of the other variable delay circuit 25 is increased in units of frames so that the input of the exclusive OR circuit 27 always has the same bit code. That is, the output of the exclusive OR circuit 27 is controlled to always be "0". Even if the delay amount of the other variable delay circuit 25 is maximized, if the output of the exclusive OR circuit 27 does not always become "0", the delay amount of the other variable delay circuit 25 is minimized, The delay amount of the one variable delay circuit 25 is similarly increased.

このようにして、排他的論理和回路27の出力が常時「
0」となったとき、制御回路30は、双方の可変遅延回
路25の遅延量の差(フレーム単位)を現用伝送路2d
と予備用伝送路3との伝送遅延差として検出する。
In this way, the output of the exclusive OR circuit 27 is always "
0'', the control circuit 30 calculates the difference (in frame units) between the delay amounts of both variable delay circuits 25 to the current transmission line 2d.
It is detected as the transmission delay difference between the transmission line 3 and the backup transmission line 3.

可変遅延メモリ33は、伝送遅延差の二倍以上でしかも
フレーム長の偶数倍のメモリ容量をもっている。制御回
路30は、現用伝送路2d側の可変遅延メモリ33につ
いて、制御信号34dによりあらかじめメモリ容量の半
分の遅延量となるように設定しておく。さらに制御回路
30は、検出した伝送遅延差により、予備用伝送路3の
遅延が現用伝送路2dの遅延より小さい場合には、現用
側の可変遅延メモリ33にあらかじめ設定されている遅
延量に新たに検出した伝送遅延差を加算し、この遅延量
を制御信号35により予備用側の可変遅延メモリ33に
設定する。また、予備用伝送路3の遅延が現用伝送路2
dの遅延より大きい場合には、現用側の可変遅延メモリ
33にあらかじめ設定されている遅延量から粗かに検出
した伝送遅延差を差し引き、この遅延量を制御信号35
により予備用側の可変遅延メモリ33に設定する。これ
により、現用伝送路2dと予備用伝送路3との間の伝送
路遅延差が、可変遅延メモリ33により吸収される。
The variable delay memory 33 has a memory capacity that is more than twice the transmission delay difference and an even number multiple of the frame length. The control circuit 30 sets the variable delay memory 33 on the current transmission line 2d side in advance so that the delay amount is half the memory capacity using the control signal 34d. Furthermore, if the delay of the backup transmission line 3 is smaller than the delay of the working transmission line 2d based on the detected transmission delay difference, the control circuit 30 adds a new delay amount to the delay amount preset in the working side variable delay memory 33. The detected transmission delay difference is added to the delay amount, and this delay amount is set in the spare variable delay memory 33 by the control signal 35. In addition, the delay of the backup transmission line 3 is greater than the delay of the working transmission line 2.
If the delay is larger than the delay of d, the roughly detected transmission delay difference is subtracted from the delay amount preset in the variable delay memory 33 on the active side, and this delay amount is used as the control signal 35.
is set in the variable delay memory 33 on the spare side. Thereby, the transmission line delay difference between the working transmission line 2d and the protection transmission line 3 is absorbed by the variable delay memory 33.

この後に、制御回路30は制御信号37により伝送路切
替スイッチ36を制御し、現用伝送路2dを予備用伝送
路3に高速に切り替える。これに続いて、制御回路32
、データリンク39を経由して制御回路13に信号を送
出し、伝送路切替スイッチ11を制御して現用伝送路2
dを切り離し、伝送路切替が完了する。
After this, the control circuit 30 controls the transmission line changeover switch 36 using the control signal 37, and switches the working transmission line 2d to the protection transmission line 3 at high speed. Following this, the control circuit 32
, sends a signal to the control circuit 13 via the data link 39, controls the transmission line changeover switch 11, and switches the current transmission line 2.
d is disconnected, and transmission line switching is completed.

第2図は情報列のフォーマットを示す。FIG. 2 shows the format of the information string.

この情報列はフレームにより構成され、個々のフレーム
は、フレーム同期ビットFおよび主情報工により構成さ
れる。可変遅延回路25では、主情報■に含まれる一以
上任意個のビットDを比較する。ただし、ビットDは各
フレームで同一ビット位置にあることが必要である。主
情報I内のすべてのビットを比較の対象とすることもで
きる。
This information string is made up of frames, and each frame is made up of a frame synchronization bit F and a main information bit. The variable delay circuit 25 compares one or more arbitrary bits D included in the main information (2). However, bit D needs to be at the same bit position in each frame. All bits in the main information I can also be compared.

第3図は各回路における情報列の位相関係を示し、(a
)は現用側のエラスティックストアメモリ20の出力、
(b)は現用側の可変遅延メモリ33の出力、(C)は
予備用側のエラスティックストアメモリ20の出力、(
d)は予備用側の可変遅延メモリ33の出力を示す。こ
の図において、Δ〜Nはフレーム、D。
Figure 3 shows the phase relationship of information strings in each circuit, and (a
) is the output of the elastic store memory 20 on the active side,
(b) is the output of the variable delay memory 33 on the active side, (C) is the output of the elastic store memory 20 on the spare side, (
d) shows the output of the variable delay memory 33 on the reserve side. In this figure, Δ~N are frames, D.

は許容伝送路間遅延差、D、は現用側の可変遅延メモリ
33による遅延1!、D2は伝送路間遅延差、D3は予
備用側の可変遅延メモリ33による遅延量であり、D3
 =DI +D2 、αは予備用側のフレームGの先頭
ビットの許容到着範囲を示す。
is the allowable delay difference between transmission paths, and D is the delay 1! due to the variable delay memory 33 on the active side. , D2 is the delay difference between transmission paths, D3 is the delay amount due to the variable delay memory 33 on the standby side, and D3
=DI +D2 , α indicates the allowable arrival range of the first bit of frame G on the spare side.

この図は、可変遅延メモリ33の容量が6フレ一ム分で
あり、予備用伝送路3の遅延が現用伝送路2dより小さ
い場合を示している。この伝送遅延差は、可変遅延メモ
リ33により吸収される。
This figure shows a case where the capacity of the variable delay memory 33 is for six frames and the delay of the backup transmission line 3 is smaller than that of the working transmission line 2d. This transmission delay difference is absorbed by the variable delay memory 33.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の伝送路切替方式は、現用
伝送路から予備用伝送路に無瞬断で伝送路を切り替える
ことができる。したがって、瞬断による伝送品質の劣化
を防止できる効果がある。
As explained above, the transmission line switching method of the present invention can switch the transmission line from the working transmission line to the protection transmission line without momentary interruption. Therefore, it is possible to prevent deterioration of transmission quality due to instantaneous interruptions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例ディジタル伝送装置のブロック構
成図。 第2図は情報列のフォーマットを示す図。 第3図は情報列の位相関係を示す図。 第4図は従来例ディジタル伝送装置のブロック構成図。 1・・・送信側装置、2.2a〜2d・・・現用伝送路
、3・・・予備用伝送路、4・・・受信側装置、10・
・・多重化変換装置、11.36・・・伝送路切替スイ
ッチ、12.14・・・インタフェース回路、13.3
0.32・・・制御回路、17・・・フレーム同期回路
、20・・・エラスティックストアメモリ、21・・・
局クロック源、24・・・切替スイッチ、25・・・可
変遅延回路、27・・・排他的論理和回路、33・・・
可変遅延メモリ、38・・・多重分離回路、39・・・
データリンク。 特許出願人 日本電信電話株式会社、−代理人 弁理士
 井 出 直 孝
FIG. 1 is a block diagram of a digital transmission device according to an embodiment of the present invention. FIG. 2 is a diagram showing the format of an information string. FIG. 3 is a diagram showing the phase relationship of information strings. FIG. 4 is a block diagram of a conventional digital transmission device. DESCRIPTION OF SYMBOLS 1... Sending side device, 2.2a-2d... Working transmission line, 3... Backup transmission line, 4... Receiving side device, 10.
...Multiplex conversion device, 11.36...Transmission path changeover switch, 12.14...Interface circuit, 13.3
0.32... Control circuit, 17... Frame synchronization circuit, 20... Elastic store memory, 21...
Station clock source, 24... Changeover switch, 25... Variable delay circuit, 27... Exclusive OR circuit, 33...
Variable delay memory, 38... Demultiplexing circuit, 39...
data link. Patent applicant: Nippon Telegraph and Telephone Corporation, agent: Naotaka Ide, patent attorney

Claims (1)

【特許請求の範囲】 1、それぞれ一定長のフレームを単位として情報列を伝
送する現用伝送路および予備用伝送路の切替手段を備え
た伝送路切替方式において、 送信側装置に、上記現用伝送路の情報列を分岐して上記
予備用伝送路に並列伝送させる手段を備え、 受信側装置に、 上記予備用伝送路から受信した情報列のフレーム位相を
上記現用伝送路から受信した情報列のフレーム位相に同
期させるエラスティックストアメモリを含むフレーム同
期手段と、このフレーム同期手段の出力する二つの情報
列の内容を比較し、これらの情報列の遅延差をフレーム
単位で測定する手段と、 この遅延差により上記予備用伝送路の遅延量を補正する
手段と を備え、 上記送信側装置と上記受信側装置との双方に、上記補正
する手段による補正の後に上記現用伝送路を切り離す手
段を備えた ことを特徴とする伝送路切替方式。
[Scope of Claims] 1. In a transmission line switching system comprising switching means for a working transmission line and a backup transmission line, each of which transmits an information string in units of frames of a fixed length, the transmitting side device is provided with a switching means for transmitting information on the working transmission line. means for branching the information sequence and transmitting it in parallel to the protection transmission line, and having the receiving side device transfer the frame phase of the information sequence received from the protection transmission line to the frame phase of the information sequence received from the working transmission line. a frame synchronization means including an elastic store memory for phase synchronization; a means for comparing the contents of two information streams outputted by the frame synchronization means and measuring a delay difference between these information streams in units of frames; means for correcting the delay amount of the backup transmission line based on the difference, and means for disconnecting the working transmission line after the correction by the correction means is provided on both the sending side device and the receiving side device. A transmission path switching method characterized by:
JP9286588A 1988-04-15 1988-04-15 System for switching transmission line Pending JPH01264427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9286588A JPH01264427A (en) 1988-04-15 1988-04-15 System for switching transmission line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9286588A JPH01264427A (en) 1988-04-15 1988-04-15 System for switching transmission line

Publications (1)

Publication Number Publication Date
JPH01264427A true JPH01264427A (en) 1989-10-20

Family

ID=14066323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9286588A Pending JPH01264427A (en) 1988-04-15 1988-04-15 System for switching transmission line

Country Status (1)

Country Link
JP (1) JPH01264427A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0447822A (en) * 1990-06-15 1992-02-18 Nec Corp Synchronization changing system
JPH05110544A (en) * 1990-06-28 1993-04-30 American Teleph & Telegr Co <Att> Method and apparatus for switching signal path and system provided with plurality of signal switching apparatuses
JPH0779208A (en) * 1993-09-06 1995-03-20 Nec Corp Noninterruptible switching system
US6680905B1 (en) 1998-10-21 2004-01-20 Fujitsu Limited Transfer path control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632435A (en) * 1986-06-20 1988-01-07 Fujitsu Ltd Circuit switching equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632435A (en) * 1986-06-20 1988-01-07 Fujitsu Ltd Circuit switching equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0447822A (en) * 1990-06-15 1992-02-18 Nec Corp Synchronization changing system
JPH05110544A (en) * 1990-06-28 1993-04-30 American Teleph & Telegr Co <Att> Method and apparatus for switching signal path and system provided with plurality of signal switching apparatuses
JPH0779208A (en) * 1993-09-06 1995-03-20 Nec Corp Noninterruptible switching system
US6680905B1 (en) 1998-10-21 2004-01-20 Fujitsu Limited Transfer path control system

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