KR930011250B1 - Line switching controller of 155 mbps class synchronous transmission system - Google Patents

Abstract

The network processor is for performing the high speed process between the optical broad casting telecommunication system. The processor comprises the control facility outputting the network process control information and taking the process control information from CPU; the telecommunication tool outputting the output signal from the high speed multi units and control units; and the receiving units (35) outputting signal into the multi processing units (1,4,19,22).

Description

Line changer of 155Mbps synchronous transmission system

1 is a block diagram of a transmission system to which the present invention is applied.

2 is a block diagram of a line changer according to the present invention.

3 is a configuration diagram of the bridge circuit and the selector circuit of FIG.

* Explanation of symbols for the main parts of the drawings

1 to 4, 19 to 22: high speed multiplexing unit

5, 18, 32: line changer 6 to 10, 12 to

16: NNIB 11: Repeater

32: CPU 33: control circuit

34: transmitter 35: receiver

36: fault monitoring circuit 37: transfer control circuit

38: transmission monitoring circuit 39: transmission input retiming circuit

40: bridge circuit 41: transmission output retiming circuit

42: reception output retiming circuit 43: selector circuit

44: reception input retiming circuit 45: reception monitoring circuit

The present invention relates to a line changer that performs switching between optical repeater transmission systems including STM-1 SOH (Synchronous Transoport Module-1 Section Overhead) signal termination, optical transmitter, repeater, optical line in 155Mbps class synchronous transmission system. .

The present invention allocates one reserve line in addition to the management line, and if one failure occurs while sharing a single reserve line to occupy the reserve line according to the transfer priority in case of failure, to improve the availability and reliability of the service channel. The purpose is to provide a track changer.

In order to achieve the above object, the present invention provides a line switching machine of a 155 Mbps synchronous transmission system comprising a high speed multiplexing unit and an operational and redundant NNI (Network Node Interface) unit for performing switching between optical relays. A control means for outputting line transfer control information by inputting the transfer control information of the control unit; Means and a receiving means connected to the control means for receiving the output of the operational and preliminary NNI units as an input and for switching to the high speed multiplexer for output.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a diagram of a transmission system to which the present invention is applied, 1 to 4, 19 to 22 are multiplexing units, 5 and 18 are line changers, 6 to 10, 12 to 16 are NNIB (Network Node Interface Board), and 11 is Each repeater is shown.

The line changers 5 and 18 according to the present invention have a high speed multiplexing unit 1 to 4 and 19 to 22 which perform the same function of the high speed multiplexing and insertion unit (Adiministration Unit) pointer insertion, and the reproduction of the received data, and the section and the line over. A line transfer function between multiple devices is performed between NNIBs (6 to 10, 12 to 16) in charge of head processing.

Lines input and output from the line changers 5 and 18 use coaxial cables to reduce noise and attenuation on the line.

Signals interfaced to the four high-speed multiplexing units (1 to 4, 9 to 22) and the line changers (5 and 18) are respectively 155 Mbps transmit and receive data signals, 155 Mbps transmit and receive clock signals, and 8 Mbps transmit and receive signals. Receive frame synchronous clock signals, and signals that are interfaced with five NNIBs (6 to 10, 12 to 17), including spare NNIBs, are 155 Mbps transmit and receive data signals, 155 Mbps transmit and receive clock signals, and 8 Mbps transmit and receive signals. Frame synchronization clock signals. In addition, transfer control information for controlling a 4: 1 transfer is provided from a central processing unit (CPU), and exchange of transfer information between two devices is performed by a multiplex section protection (MSP) channel composed of K1 / K2 bytes included in STM-1. CCITT G. 783 Recommendations), where this information is transmitted on all operational and reserve lines, but is configured so that the receiving side receives mainly MSP channels on the reserve line.

2 is a configuration diagram of the line changer according to the present invention, 31 is a CPU, 32 is a line changer, 33 is a control circuit, 34 is a transmitter, 35 is a receiver, 36 is a fault monitoring circuit, 37 is a transfer control circuit, 38 Is a transmission monitoring circuit, 39 is a transmission input retiming circuit, 40 is a bridge circuit, 41 is a transmission output retiming circuit, 42 is a reception output retiming circuit, 43 is a selector circuit, 44 is a reception input retiming circuit, and 45 is a reception. Each monitoring circuit is shown.

The line changer 32 according to the present invention includes a control circuit 33, a transmitter 34, and a receiver 35, as shown in FIG. 2, and the control circuit 33 is a switching control circuit. (37) and a failure monitoring circuit (36), wherein the transmission section (34) includes a transmission monitoring circuit (38), a transmission input retiming circuit (39), a bridge circuit (40), and a transmission output retiming circuit (41). The receiver 35 is composed of a reception monitoring circuit 45, a reception input retiming circuit 44, a selector circuit 43 and a reception output retiming circuit 42.

The control circuit unit 33 functions to output the line transfer control information by using the transfer control information input from the CPU 31, and the transmission unit 34 is the control circuit unit 33 and the high speed multiplexing unit (1 to 1). 4, 19 to 22 as an input to the operating and preliminary NNIB (6 to 10, 12 to 16) to function to bridge the output, and the receiver 35 is operated and the control circuit 33 The output of the preliminary NNIBs 6 to 10, 12 to 16 is used as an input, and is switched to the high speed multiplexing units 1 to 4 and 19 to 22 to output.

The transfer control circuit 37 is connected to the CPU 31, the bridge circuit 40 of the transmitter 34, and the selector circuit 43 of the receiver 35, and transfer control information received from the CPU 31. In order to control the bridge circuit 40 and the selector circuit 43 to control the ECL (Emitter Coupled Logic) level to control the transmitter 34 and 43 at the same time to have a bidirectional switching characteristics .

The failure monitoring circuit 36 is connected to the transmission monitoring circuit 38 of the CPU 31, the transmission unit 34, and the reception monitoring circuit 45 of the reception unit 35 to transmit and receive the monitoring circuits 38 and 45. ) Is converted into a TTL (Transistor Transistor Logic) level to output to the CPU (31).

The transmission monitoring circuit 38 is connected to the failure monitoring circuit 36 and the transmission input retiming circuit 39 to input a 155 Mbps clock signal of the outputs of the high-speed multiplexing units 1 to 4 and 19 to 22 as inputs. After monitoring the fault, the 155Mbps clock signal and the signal indicating the fault condition are output. That is, if there is an error by monitoring the 155Mbps clock signal among each input signal, it is configured to transition from '0' state to '1' state and inform the CPU, which is the case when the signal passing through the line changer 32 fails. This is to determine the fault location.

The transmission input retiming circuit 39 functions to retime the output of the high-speed multiplexing units 1 to 4, 19 to 22 input through the transmission monitoring circuit 38 as an input.

The bridge circuit 40 bridges and outputs the signal output from the transmission input retiming circuit 39 according to the line transfer control information output from the transfer control circuit 37. In the normal state, operation channel 1 is output. And the reserve line, and operating channels 2 to 4 are separated from the reserve line, so that in case of a failure, the failed channel having the highest switching priority is connected to the reserve line.

The transmission output retiming circuit 41 retimes and outputs the output of the bridge circuit 40.

The reception monitoring circuit 45 is connected to the failure monitoring circuit 36 and the reception input retiming circuit 44 to input a 155 Mbps clock signal of the outputs of the operational and preliminary NNIBs 6 to 10 and 12 to 16. After the fault monitoring, a 155Mbps clock signal and a signal indicating the fault condition are output.

The reception input retiming circuit 44 functions to retime using the outputs of the operational and preliminary NNIBs 6 to 10, 12 to 16 inputted through the reception monitoring circuit 45 as inputs.

The selector circuit 43 selects and outputs a signal output from the reception input retiming circuit 44 in a switching operation according to the switching control information output from the switching control circuit 37. That is, in the normal state of the operation lines 1 to 4 and the reserve line, the operation channel (1-4) is connected to the operation line, and the operation channel connected to the failure line with the highest switching priority in case of failure is reserved. Be connected to the track.

The receiving output retiming circuit 42 retimes and outputs the output of the selector circuit 43.

The transmission and reception input signals are input to the transmission and reception input retiming circuits 39 and 44 for synchronizing the respective signals via the transmission and reception monitoring circuits 38 and 45. In the case of a transmission signal, the signal passing through the transmission input retiming circuit 39 passes through the bridge circuit 40 and is output in synchronization with the transmission output retiming circuit 41. In the case of the reception signal, the signal passing through the reception input retiming circuit 44 passes through the circuit 43 and is output in synchronization with the reception output retiming circuit 42.

3 is a configuration diagram of the bridge circuit 40 and the selector circuit 43 in FIG. 2, and 51 to 58 show an ECL gate, which is a logic gate suitable for a high speed signal.

Since the line changer 32 operates in a four-to-one switching structure of bidirectional return as a whole, the bridge circuit 40 is composed of logic gates 51 to 54 so that the operation line 1 and the reserve line are in a normal state. It is bridged to form a one-to-one congestion structure, and the fault generating line occupies the reserve line when a failure occurs. The selector circuit 43 switches a logic gate to switch the output signal of the receiving input retiming circuit 44. 55 to 58, as shown in FIG.

The present invention configured and operated as described above may provide a service without deterioration in transmission performance by providing a service for providing a service line as a reserve line in case of a failure by providing a reserve line in addition to a service line providing a service. Applicable effect.

Claims (4)

155Mbps class synchronous type comprising high speed multiplexing units (1 to 4,10 to 22) and operational and redundant NNI (6 to 10, 12 to 16) units for switching between optical relays In line changer of transmission system; Control means 33 for outputting line transfer control information by inputting transfer control information from a CPU, and the high speed multiplexing units 1 to 4, 19 to 22 and control means 33 connected to the control means 33; Is connected to the control means 33 and the transmission means 34 for bridging and outputting to the operational and preliminary NNI units 6 to 10, 12 to 16, and the control means 33. And a receiving means (35) for switching and outputting to the high-speed multiplexing unit (1 to 4, 19 to 22) with the outputs of the sections (6 to 10, 12 to 16) as inputs. The switching control means (37) of claim 1, wherein the control means (33) converts the input switching control information to an emitter coupled logic (ECL) level and outputs it to the transmission means (34) and the receiving means (35). And fault monitoring means 36 connected to the transmitting means 34 and the receiving means 35 to convert the output of the transmitting means 34 and the receiving means 35 to a TTL (Transistor Transistor Logic) level and output the same. A track changer, characterized in that consisting of). The transmission monitoring according to claim 1, wherein the transmission means (34) receives a 155 Mbps output signal among the outputs of the high speed multiplexers (1 to 4, 19 to 22) and outputs a 155 Mbps clock signal and a fault condition after the fault monitoring. A transmission input link connected to the means 38 and the transmission monitoring means 38 to output the timing of the output of the high-speed multiplexing units 1 to 4, 19 to 22 inputted through the transmission monitoring means 38; A bridge means (40) connected to the timing means (39), the transmission input retiming means (39), and the control means (33) to bridge and output in accordance with the line transfer control information output from the control means (33), and A transmission output retiming means 41 connected to the bridge means 40 to retime the output of the bridge means 40 and output to the operational and preliminary NNIs 6 to 10, 12 to 16; Characterized by track changer. The reception means (35) according to claim 1, wherein the receiving means (35) receives a 155 Mbps clock signal from among the operation and outputs of the NNI units (6 to 10, 12 to 16) and outputs a 155 Mbps clock signal and a fault state after fault monitoring. It is connected to the monitoring means 45 and the reception monitoring means 45, and outputs by retiming the output of the operation and preliminary NNI units 6 to 10, 12 to 16 inputted through the reception monitoring means 45. Selecting means connected to the receiving input retiming means 44, the receiving input retiming means 44 and the control means 33 to switch and output in accordance with the line transfer control information output from the control means 33 ( 43) and a reception output retiming means 42 connected to the selection means 43 to retime the output of the selection means 43 and output to the high speed multiplexers 1 to 4, 19 to 22. A track changer, characterized in that configured.