JPH01175023U - - Google Patents
Info
- Publication number
- JPH01175023U JPH01175023U JP1988070513U JP7051388U JPH01175023U JP H01175023 U JPH01175023 U JP H01175023U JP 1988070513 U JP1988070513 U JP 1988070513U JP 7051388 U JP7051388 U JP 7051388U JP H01175023 U JPH01175023 U JP H01175023U
- Authority
- JP
- Japan
- Prior art keywords
- delay
- signal
- circuit
- signals
- line circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は、本考案の一実施例の信号遅延回路の
構成を示すブロツク図である。第２図は、第１図
の実施例のデコード回路１０２および信号選択回
路１０４の回路例を示す回路図である。第３図は
、第１図の実施例のタイムチヤートである。第４
図は、本考案の他の実施例の信号遅延回路の構成
を示すブロツク図である。第５図は、第４図の実
施例のラツチ回路４０３と、信号選択回路１０４
の回路例を示す回路図である。第６図は、第４図
の実施例のタイムチヤートである。第７図は従来
の信号遅延回路のブロツク図である。
１……入力信号、２……デイレイライン回路、
３……遅延出力信号、４……遅延回路出力信号、
５……パツケージ、６……ストラツプ端子板、１
０１……選択信号、１０２……デコード回路、１
０３……デコード信号、１０４……信号選択回路
、２１……アンドゲート、２０２……オアゲート
、４０１……選択信号、４０２……ラツチタイミ
ング信号、４０３……ラツチ回路、４０４……ラ
ツチ信号。
FIG. 1 is a block diagram showing the configuration of a signal delay circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the decoding circuit 102 and signal selection circuit 104 of the embodiment shown in FIG. FIG. 3 is a time chart of the embodiment shown in FIG. Fourth
The figure is a block diagram showing the configuration of a signal delay circuit according to another embodiment of the present invention. FIG. 5 shows the latch circuit 403 and signal selection circuit 104 of the embodiment of FIG.
FIG. 2 is a circuit diagram showing an example of the circuit. FIG. 6 is a time chart of the embodiment of FIG. 4. FIG. 7 is a block diagram of a conventional signal delay circuit. 1...Input signal, 2...Delay line circuit,
3...Delayed output signal, 4...Delay circuit output signal,
5...Package, 6...Strap terminal board, 1
01...Selection signal, 102...Decoding circuit, 1
03... Decode signal, 104... Signal selection circuit, 21... AND gate, 202... OR gate, 401... Selection signal, 402... Latch timing signal, 403... Latch circuit, 404... Latch signal.
Claims (1)
と、該デイレイライン回路の遅延信号の内、所要
の遅延時間の遅延信号を選択する手段とを同一パ
ツケージに納めたことを特徴とした信号遅延回路
。 A signal delay circuit characterized in that a delay line circuit that outputs a plurality of delay signals and means for selecting a delay signal with a required delay time from among the delay signals of the delay line circuit are housed in the same package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988070513U JPH01175023U (en) | 1988-05-27 | 1988-05-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988070513U JPH01175023U (en) | 1988-05-27 | 1988-05-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01175023U true JPH01175023U (en) | 1989-12-13 |
Family
ID=31295754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988070513U Pending JPH01175023U (en) | 1988-05-27 | 1988-05-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01175023U (en) |
-
1988
- 1988-05-27 JP JP1988070513U patent/JPH01175023U/ja active Pending
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