JPH0386669U - - Google Patents
Info
- Publication number
- JPH0386669U JPH0386669U JP14774789U JP14774789U JPH0386669U JP H0386669 U JPH0386669 U JP H0386669U JP 14774789 U JP14774789 U JP 14774789U JP 14774789 U JP14774789 U JP 14774789U JP H0386669 U JPH0386669 U JP H0386669U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- input
- output
- circuit
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Synchronizing For Television (AREA)
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図ａはタイマを構成するシフトレジ
スタのブロツク図。第２図ｂはトルグフリツプフ
ロツプのブロツク図。第３図はこの考案の一実施
例の作用の説明に供するタイミング図。第４図は
従来例の回路図。
１および３１……排他倫理和回路、２……タイ
マ、２１〜２５および３２……Ｄフリツプフロツ
プ、３……トルグフリツプフロツプ。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2a is a block diagram of a shift register constituting a timer. FIG. 2b is a block diagram of a torque flip-flop. FIG. 3 is a timing diagram for explaining the operation of one embodiment of this invention. FIG. 4 is a circuit diagram of a conventional example. 1 and 3 1 ... exclusive sum circuit, 2 ... timer, 2 1 to 2 5 and 3 2 ... D flip-flop, 3 ... torque flip-flop.
Claims (1)
同期信号分離回路であつて、複合同期信号を一方
の入力とする排他論理和回路と、該排他論理和回
路の出力でリセツトされ、リセツトが解除された
後、一定数のクロツクパルスの入力によつて出力
を発生するタイマ手段と、タイマ手段からの出力
によりトグル動作を行なうトルグフリツプフロツ
プとを備え、トグルフリツプフロツプの出力を前
記排他論理和回路の他方の入力としたことを特徴
とする垂直同期信号分離回路。 A vertical synchronization signal separation circuit that separates a vertical synchronization signal from a composite synchronization signal, which includes an exclusive OR circuit that receives the composite synchronization signal as one input, and is reset and released from reset by the output of the exclusive OR circuit. After that, it is provided with a timer means that generates an output in response to input of a certain number of clock pulses, and a toggle flip-flop that performs a toggle operation based on the output from the timer means, and the output of the toggle flip-flop is subjected to the exclusive OR operation. A vertical synchronization signal separation circuit characterized in that the other input of the circuit is used as the other input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14774789U JP2530025Y2 (en) | 1989-12-25 | 1989-12-25 | Vertical sync signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14774789U JP2530025Y2 (en) | 1989-12-25 | 1989-12-25 | Vertical sync signal separation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0386669U true JPH0386669U (en) | 1991-09-02 |
| JP2530025Y2 JP2530025Y2 (en) | 1997-03-26 |
Family
ID=31694250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14774789U Expired - Lifetime JP2530025Y2 (en) | 1989-12-25 | 1989-12-25 | Vertical sync signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2530025Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101500641B1 (en) * | 2014-03-13 | 2015-03-09 | 코오롱인더스트리 주식회사 | Multipurpose bag |
-
1989
- 1989-12-25 JP JP14774789U patent/JP2530025Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101500641B1 (en) * | 2014-03-13 | 2015-03-09 | 코오롱인더스트리 주식회사 | Multipurpose bag |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2530025Y2 (en) | 1997-03-26 |
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