JPH02100345U - - Google Patents
Info
- Publication number
- JPH02100345U JPH02100345U JP810489U JP810489U JPH02100345U JP H02100345 U JPH02100345 U JP H02100345U JP 810489 U JP810489 U JP 810489U JP 810489 U JP810489 U JP 810489U JP H02100345 U JPH02100345 U JP H02100345U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- timer
- input
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
- Interconnected Communication Systems, Intercoms, And Interphones (AREA)
Description
第１図は、本考案の信号変換ユニツトのブロツ
ク構成図、第２図はその動作を説明するタイミン
グチヤート、第３図はその外観の斜視図、第４図
はその詳細な回路例図、第５図及び第６図は従来
の信号変換ユニツトの回路例図及び構造を説明す
る図である。
符号の説明、１ａ……信号入力回路、Ｔ１……
第１の設定時間、Ｔ２……第２の設定時間、１ｂ
……第１のタイマー回路、１ｃ……第２のタイマ
ー回路、１ｄ……信号出力回路。
Fig. 1 is a block configuration diagram of the signal conversion unit of the present invention, Fig. 2 is a timing chart explaining its operation, Fig. 3 is a perspective view of its appearance, Fig. 4 is a detailed circuit example diagram thereof, 5 and 6 are diagrams illustrating circuit examples and structures of conventional signal conversion units. Explanation of symbols, 1a...Signal input circuit, T1...
First setting time, T2...Second setting time, 1b
...First timer circuit, 1c...Second timer circuit, 1d...Signal output circuit.
Claims (1)
号入力回路の出力信号によつて起動されて各々第
１の設定時間及び第２の設定時間だけタイマー信
号を出力する第１のタイマー回路及び第２のタイ
マー回路と、上記第１のタイマー回路のタイマー
信号を受けて信号を出力する信号出力回路とを備
えた信号変換ユニツトであつて、 上記信号入力回路に信号が入力されると、上記
第２のタイマー回路が起動されて上記第２の設定
時間だけ上記第１のタイマー回路にタイマー信号
を出力して該第１のタイマー回路をリセツトし、
該第２のタイマー回路がタイムアツプすると、上
記第１のタイマー回路のリセツトを解除した後、
該第１のタイマー回路は上記信号入力回路の出力
信号で起動されて上記第１の設定時間だけ上記信
号出力回路に信号を出力して、該信号出力回路か
ら上記第１の設定時間だけ信号を出力する構成と
したことを特徴とする、信号変換ユニツト。[Claims for Utility Model Registration] A signal input circuit that receives an input signal, and is activated by the output signal of the signal input circuit and outputs a timer signal for a first set time and a second set time, respectively. A signal conversion unit comprising a first timer circuit, a second timer circuit, and a signal output circuit that receives a timer signal from the first timer circuit and outputs a signal, wherein the signal is input to the signal input circuit. When input, the second timer circuit is activated and outputs a timer signal to the first timer circuit for the second set time to reset the first timer circuit;
When the second timer circuit times out, after canceling the reset of the first timer circuit,
The first timer circuit is activated by the output signal of the signal input circuit, outputs a signal to the signal output circuit for the first set time, and outputs the signal from the signal output circuit for the first set time. A signal conversion unit characterized by being configured to output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP810489U JPH02100345U (en) | 1989-01-26 | 1989-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP810489U JPH02100345U (en) | 1989-01-26 | 1989-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02100345U true JPH02100345U (en) | 1990-08-09 |
Family
ID=31213685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP810489U Pending JPH02100345U (en) | 1989-01-26 | 1989-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02100345U (en) |
-
1989
- 1989-01-26 JP JP810489U patent/JPH02100345U/ja active Pending