JPH01146627U

JPH01146627U -

Info

Publication number: JPH01146627U
Application number: JP4034588U
Authority: JP
Priority date: 1988-03-29
Filing date: 1988-03-29
Publication date: 1989-10-09

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示すブロツク図、第
２図は上記実施例における各部の動作波形を示す
タイムチヤート、第３図ａは従来のデジタルフイ
ルタを示す回路図、第３図ｂは上記従来例の動作
を説明するための波形図である。１０……リセツト回路を構成するフリツプフロ
ツプ、１２……トリガ回路のフリツプフロツプ回
路、１３……トリガ回路の排他的論理和回路、１
５……フリツプフロツプ回路。 Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing the operating waveforms of each part in the above embodiment, Fig. 3a is a circuit diagram showing a conventional digital filter, and Fig. 3b is a FIG. 3 is a waveform diagram for explaining the operation of the conventional example. 10...Flip-flop constituting the reset circuit, 12...Flip-flop circuit of the trigger circuit, 13...Exclusive OR circuit of the trigger circuit, 1
5...Flip-flop circuit.

Claims

[Claims for Utility Model Registration] (1) A flip-flop circuit having a signal input terminal, a signal output terminal, and a clock terminal, a digital signal being input to the signal input terminal, and the signal output terminal serving as a filter output terminal; The clock circuit has a clock circuit connected to the clock terminal, and the clock circuit checks whether or not there is a change in the state of the digital signal every time the level of the clock pulse changes to one level. A trigger circuit that generates an output in synchronization with the timing of this change, and a trigger circuit that checks whether or not there is a change in the state of the digital signal every time the level of the clock pulse changes to the other level, and when a state change occurs, the clock pulse changes. A digital filter comprising a reset circuit that eliminates the output in synchronization with timing, and supplies the output to the clock terminal of the flip-flop circuit. (2) The reset circuit is a flip-flop circuit that receives a digital signal and an inverted signal of a clock pulse, the output of which is supplied to a flip-flop circuit of a trigger circuit, and the trigger circuit is an exclusive OR circuit that receives the outputs of both flip-flop circuits. 2. The digital filter according to claim 1, wherein the digital filter changes the potential level of a clock terminal of a flip-flop circuit connected to the clock circuit in synchronization with a change in the output of the exclusive OR circuit.