JPS61171332U - - Google Patents
Info
- Publication number
- JPS61171332U JPS61171332U JP5364685U JP5364685U JPS61171332U JP S61171332 U JPS61171332 U JP S61171332U JP 5364685 U JP5364685 U JP 5364685U JP 5364685 U JP5364685 U JP 5364685U JP S61171332 U JPS61171332 U JP S61171332U
- Authority
- JP
- Japan
- Prior art keywords
- external clock
- signal
- cmi signal
- decoder
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例を示すブロツク図、
及び第２図は本実施例の動作タイミング図である
。
１……遅延素子、２……論理回路、３……外部
クロツク発生回路、４……カウンタ、５……デコ
ーダ、６，７……フリツプフロツプ。
FIG. 1 is a block diagram showing an embodiment of the present invention.
and FIG. 2 are operation timing diagrams of this embodiment. 1...Delay element, 2...Logic circuit, 3...External clock generation circuit, 4...Counter, 5...Decoder, 6, 7...Flip-flop.
Claims (1)
生する外部クロツク発生回路と、該外部クロツク
をカウントし前記ＣＭＩ信号の立下りエツジでリ
セツトされるカウンタと、該カウンタの出力をデ
コードするデコーダとを有し、該デコーダの出力
に基づき前記ＣＭＩ信号をサンプリングしてＮＲ
Ｚ信号を得ることを特徴とするＣＭＩ信号デコー
ド回路。 It has an external clock generation circuit that generates an external clock with a higher frequency than the CMI signal, a counter that counts the external clock and is reset at the falling edge of the CMI signal, and a decoder that decodes the output of the counter, The CMI signal is sampled based on the output of the decoder and NR
A CMI signal decoding circuit characterized by obtaining a Z signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985053646U JPH0323714Y2 (en) | 1985-04-12 | 1985-04-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985053646U JPH0323714Y2 (en) | 1985-04-12 | 1985-04-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61171332U true JPS61171332U (en) | 1986-10-24 |
| JPH0323714Y2 JPH0323714Y2 (en) | 1991-05-23 |
Family
ID=30574707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985053646U Expired JPH0323714Y2 (en) | 1985-04-12 | 1985-04-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323714Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS592216A (en) * | 1982-06-25 | 1984-01-07 | Fujitsu Ltd | Data demodulator |
-
1985
- 1985-04-12 JP JP1985053646U patent/JPH0323714Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS592216A (en) * | 1982-06-25 | 1984-01-07 | Fujitsu Ltd | Data demodulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0323714Y2 (en) | 1991-05-23 |
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