JPS6258942U - - Google Patents
Info
- Publication number
- JPS6258942U JPS6258942U JP14981585U JP14981585U JPS6258942U JP S6258942 U JPS6258942 U JP S6258942U JP 14981585 U JP14981585 U JP 14981585U JP 14981585 U JP14981585 U JP 14981585U JP S6258942 U JPS6258942 U JP S6258942U
- Authority
- JP
- Japan
- Prior art keywords
- narrow width
- pulses
- transmitting
- width pulses
- transmission system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図、第３図は送信側のタイミング・カウ
ンタ、ビツト・カウンタの状態遷移図、第４、第
５図は受信側のタイミング・カウンタ、ビツト・
カウンタの状態遷移図、第６図は第１図における
各部分における動作波形図、第７図は従来システ
ムにおける伝送信号を示す波形図である。
１…送信側エンコーダ、２…伝送路、３…受信
側デコーダ、１１…符号化回路、１２…送信クロ
ツク抽出ユニツト、１３…トランスミツタ、３１
…レシーバ、３２…復号化回路、３３…受信クロ
ツク抽出ユニツト。
Figure 1 is a configuration block diagram showing an embodiment of the present invention, Figures 2 and 3 are state transition diagrams of the timing counter and bit counter on the transmitting side, and Figures 4 and 5 are timing diagrams on the receiving side.・Counter, bit・
FIG. 6 is a state transition diagram of the counter, FIG. 6 is an operation waveform diagram of each part in FIG. 1, and FIG. 7 is a waveform diagram showing transmission signals in the conventional system. DESCRIPTION OF SYMBOLS 1... Transmission side encoder, 2... Transmission line, 3... Receiving side decoder, 11... Encoding circuit, 12... Transmission clock extraction unit, 13... Transmitter, 31
...Receiver, 32...Decoding circuit, 33...Reception clock extraction unit.
Claims (1)
とをシリアル信号として受信側に伝送させる調歩
同期式のシリアル・データ伝送システムであつて
、前記送信側にスタート・ビツトを幅の狭い複数
のパルスに変換して伝送する手段を設けると共に
、前記受信側に幅の狭い複数のパルスを受信した
場合それをスタート・ビツトとして受信動作を行
う手段を設けたことを特徴とするシリアル・デー
タ伝送システム。 This is an asynchronous serial data transmission system in which a start bit and data bits are transmitted as serial signals from the transmitting side to the receiving side, and the transmitting side converts the start bits into multiple narrow pulses. 1. A serial data transmission system characterized by comprising: means for transmitting a plurality of narrow width pulses; and means for performing a reception operation using a plurality of narrow width pulses as a start bit when the reception side receives a plurality of narrow width pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981585U JPS6258942U (en) | 1985-09-30 | 1985-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14981585U JPS6258942U (en) | 1985-09-30 | 1985-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6258942U true JPS6258942U (en) | 1987-04-11 |
Family
ID=31065377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14981585U Pending JPS6258942U (en) | 1985-09-30 | 1985-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6258942U (en) |
-
1985
- 1985-09-30 JP JP14981585U patent/JPS6258942U/ja active Pending
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