JPH0511817B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a device that performs start-stop synchronization with data signals arriving from a data terminal device or other devices, temporarily stores the data signals, and transmits them as lines are synchronized. Use as.

〔overview〕

In a circuit that performs asynchronous synchronization with an input signal, the present invention divides a timing signal whose frequency is N times the bit rate of the input signal and uses it as a synchronization signal, and uses the divided phase for this N frequency division by asynchronous synchronization. By setting this, the asynchronous synchronization circuit can be simplified, and even long data signals can be transmitted using asynchronous synchronization.

[Conventional technology]

Conventionally, when performing asynchronous data transmission, a start signal bit ``0'' is added to the front of every 8 bits of the character signal, and a stop signal bit ``1'' is added to the rear, and synchronization is achieved with the start signal bit for each character signal. The device is known.

[Problem that the invention seeks to solve]

However, this type of conventional system has the disadvantage that the effective transmission efficiency of the data to be transmitted is reduced because it is transmitted in character signal units. That is,
In start-stop synchronization, data signals expressed in character signal units could not be transmitted unless synchronization was achieved.

The present invention solves this problem, and aims to provide an asynchronous synchronization circuit that can establish correct synchronization even for long data signals using a simple asynchronous synchronization circuit.

[Means for solving problems]

The present invention provides a write buffer circuit for temporarily accumulating input signals, a read buffer circuit for transferring and temporarily accumulating the contents of the write buffer circuit, and reading out the contents in synchronization with the output signal; In an asynchronous signal transmission device comprising a write address circuit that generates a write address for a buffer circuit, and synchronization means that controls this write address circuit in synchronization with an input signal, the synchronization means A frequency divider circuit divides the timing signal N times the bit rate of the signal (N is an integer of 2 or more) and supplies it to the counting input of the write address circuit, and the input signal has the same logical value over the specified bits. a stop signal detection circuit for detecting a stop signal to detect continuity; a means for detecting a logical value opposite to the logical value following the stop signal; and a frequency dividing circuit for dividing the frequency at the output timing of the detecting means. The present invention is characterized by comprising circuit means for controlling the phase.

[Effect]

Consecutive bits of the same logical value ``1'' or ``0'' of a specified length or longer and the next inverted 1-bit signal are detected as start signal bits, and the frequency division phase is thereby controlled to prevent bit synchronization from occurring. Make it. Therefore, it is possible to transmit fairly long data as one block of data.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

An asynchronous input signal arrives at the input terminal 1 . It includes a write buffer circuit 7 that temporarily stores this input signal, and a read buffer circuit 9 that transfers and temporarily stores the contents of the write buffer circuit 7 and reads them out in synchronization with the output side.

The write buffer circuit 7 is controlled by a write address circuit 6 which generates a write address, and this write address circuit 6 is controlled in synchronization with an input signal. A feature of the present invention is the synchronization means for this purpose.

This synchronization means includes a frequency dividing circuit 11 which divides the timing signal 3 which is N times the bit rate of the input signal (N is an integer of 2 or more) and supplies it to the counting input of the write address circuit; A stop signal detection circuit 10 detects a stop signal that detects that the same logical value continues over a specified bit.
, an OR circuit 14 for detecting the opposite logic value of the logic value following the stop signal, and control circuit means for controlling the frequency division phase of the frequency divider circuit at the output timing of the OR circuit.

This control circuit means includes an AND circuit 13, a D-type flip-flop 15 which takes the output of the AND circuit 13 as a D input and the timing signal 3 as a clock input, and an output of the AND circuit 13 with the output of the flip-flop 15 as a clock input. a flip-flop 12 connected to one input of the flip-flop 12;

This operation will be explained below.

A stop signal bit detection circuit 10 counts the continuous signal "1" in the input data signal by x bits (x is a set integer). As a result, the detection signal "0" is output to the OR circuit 14, and it waits for reception of the start signal bit. When the start signal bit is received, the output of the OR circuit 14 is set to "0", and the output of the AND circuit 1 is set to "0".
The output of the register circuit 15 is set to "0" by the timing signal 3 which is N times the input data rate from the input terminal 18. This resets the frequency dividing circuit 11. The rising edge of the sampling signal 2 is output at the time of counting N/2 times by the timing signal 3 which is N times the input data rate from the input terminal 18. The output of the OR circuit 14 is set to "1" at the next bit timing of the continuous signal "1" which is longer than the specified length of the asynchronous data, and the timing signal 3 of N times the input data rate from the input terminal 18 causes the register 15 to be set to "1". The output of is returned to "1", and the write address counter 6 is operated by the sampling signal 2 which is the output of the free-running frequency dividing circuit 11 by the timing signal 3 which is N times the input data rate from the input terminal 18. let As a result, the input signal 1, which is asynchronous data, is latched by the write buffer circuit 7. The read address counter 8, which is controlled so as not to match the count value of the write address counter 6, is operated by the synchronous retiming signal 5 input from the input terminal 17, and the read buffer circuit 9 reads the synchronous retiming data 4. Output to output terminal 19.

FIG. 2 is a time chart of an asynchronous transmission format illustrating an embodiment of the present invention. FIG. 2 shows that the phase of the sampled signal 2 is corrected by the start signal bit immediately after the continuous signal of "1" of x bits or more of the asynchronous data 1 from the accommodated terminal device.

FIG. 3 is a detailed time chart of the sampled signal 2. FIG. 3 shows a time chart of a sampled signal reset by a start signal bit in asynchronous transmission according to the present invention. In Figure 3, counting is started from the beginning of the start signal bit of asynchronous data 1 using a timing signal 3 that is N times the input data rate that is synchronized with the oscillation circuit of the transmission device, and is counted N/2 times. It is assumed that a sampled signal 2 having a rising edge is created at a time point.

〔Effect of the invention〕

As explained above, according to the present invention, correct synchronization can be established with a simple circuit. Therefore, even data with a long bit length can be correctly latched in almost the same way as in the case of synchronous transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transmission device according to an embodiment of the present invention. Figure 2 is a time chart of the data transmission format in asynchronous transmission. Figure 3 is a detailed time chart of the sampled signal. 1...Input signal, 2...Sampling signal, 3...Timing signal N times the input data rate, 4...Synchronous retiming data, 5...Synchronous retiming signal, 6...Write address Counter, 7...
Write buffer circuit, 8... Read address counter, 9... Read buffer circuit, 10... Stop signal detection circuit, 11... Frequency divider circuit, 12... Register circuit, 13... AND circuit, 14... OR Circuit, 15...Register circuit, 16, 17, 18...
...output terminal, 19...output terminal.

Claims (1)

[Claims] 1. Write buffer circuit 7 that temporarily stores input signals
a read buffer circuit 9 that transfers and temporarily stores the contents of this write buffer circuit and reads them out in synchronization with the output signal; and a write address circuit that generates a write address for the write buffer circuit. 6, and synchronization means for controlling this write address circuit in synchronization with the input signal, wherein the synchronization means has a bit rate N times the bit rate of the input signal (N is 2 or more). a frequency divider circuit 11 which divides the timing signal (an integer of ) by N and supplies it to the counting input of the write address circuit.
a stop signal detection circuit 10 for detecting a stop signal that detects that the same logical value continues over a specified number of bits in the input signal; means 14 for detecting a logical value opposite to the logical value following the stop signal; Circuit means 12, 13 for controlling the frequency dividing phase of the frequency dividing circuit based on the output timing of the detecting means;
15. An asynchronous signal transmission device characterized by comprising: