JPH0141254Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a data transmission device that facilitates mutual data communication in a multi-drop communication system in which communication between a plurality of computers is carried out via a single transmission line.

In order to realize communication between a plurality of computers, for example, a multi-drop computer system is configured. FIG. 1 shows this multi-drop communication system, in which a plurality of computers 11 ₁ to 11 _o are all connected to one transmission line 12. The computers 11 ₁ to 11 _o each include a transmitting and receiving circuit 13 that transmits and receives data to and from the transmission line 12, a central processing unit 14 that performs various arithmetic processing, and the like.
The transmission line 12 and the transmission/reception circuit 13 are as follows:
They are coupled by a pulse transformer 15 to achieve electrical isolation for data transmission and reception. Here, 16 is a terminating resistor of the transmission line 12.

The waveform of data transmitted in such a computer system differs depending on how synchronization data for synchronizing the computers is transmitted to the receiving end. Figure 2 shows various communication codes RZ (Return to
Zero), NRZI (Non Return to Zero)
Inversion), AMI (Alternate Mark Inversion)
If "1" and "0" exist in these transmitted data for a long period of time, the transmitted waveform will no longer change to "10" and "01", and the receiving end will not be able to perform sampling for synchronization. Clocks become difficult to extract. Therefore, “1” or “0” corresponds to 5 data (5 sampling clocks)
A method of forcibly superimposing synchronization data with “0” or “1” on the main data itself when continuous,
As shown in FIG. 3, a data format is used in which both main data and synchronization data (Synchronous signal) are transmitted continuously.

Here, the Sync signal mentioned above is often a pattern of "010101" that makes it easy for the sampling clock at the receiving end to synchronize, and the receiving end to which this Sync signal is supplied accurately samples each bit information unit of the received data. Therefore, synchronization with the receiving sampling clock is performed using, for example, a digital phase synchronization circuit as shown in FIG.

The above digital phase synchronization circuit is the central processing unit 1
The data transmitted through the transmission line 12 is received by the transmitter/receiver circuit 13 and supplied to the detector 20 . This detector 20
is for detecting “1” of the Sync signal included in the received data, and this detected signal is supplied to the comparator 21. This comparator 21 compares the number of pulses supplied to the B terminal from the counter 22 in units of 32 counts, for example, with a set value set to the A terminal in units of 16 counts, for example, and the comparison operation of this comparator 21 is performed in synchronization with the detection signal from the detector 20. If the pulse count of the counter 22 is advanced, the comparator 21 is connected to the phase advance F/F2.
3 is turned on to operate the erase pulse gate 24, and if the pulse count of the counter 22 is delayed, the slow phase F/F 25 is turned on and the addition pulse gate 26 is operated. That is, as the pulse count of the counter 22 progresses, the erase pulse gate 24 reduces the number of pulses from the oscillator 27 and delays the count of the counter 22. Also, the counter 22
If the pulse count of is delayed, addition pulse gate 2
6 increases the number of pulses from the oscillator 27 and advances the count of the counter 22. As a result, the counter 22 outputs a sampling clock with an accurate count value synchronized with the Sync signal of the received data.

In other words, each computer ₁₁ operating asynchronously
The sampling clocks 11o to _11o are synchronized by a digital phase synchronization circuit provided at the receiving end each time data transmitted together with a Sync signal etc. is transmitted to the transmission line 12.

However, if the sampling clocks of each computer were synchronized every time data was transmitted,
For example, if data transmission is interrupted for a long time, the sampling clocks of each computer will become largely out of synchronization during that time. Therefore, when restarting data transmission after a long interruption of data transmission,
Even if a Sync signal is sent along with the data, it will be difficult to regain synchronization of the sampling clock during the time the Sync signal is being sent, making it impossible to reliably sample the data at the receiving end. Become.

This idea was made in order to solve the problems mentioned above. For example, even if data transmission is interrupted for a long time, the sampling clocks of each computer will not be out of synchronization. An object of the present invention is to provide a data transmission device that enables reliable sampling of data at a receiving end when data transmission is resumed.

That is, the data transmission device according to this invention has 1
In a computer system in which multiple computers are connected in parallel to a main transmission line and synchronized with each computer's sampling clock, a count is counted after a preset time has elapsed from the time when data is no longer transmitted to the transmission line. The sampling clock is equipped with a synchronization command counter that is turned up, and a synchronization circuit that synchronizes the sampling clock based on synchronization data that is transmitted to the transmission line in response to a command from the synchronization command counter.

An embodiment of this invention will be described below with reference to the drawings.

FIG. 5 shows the configuration of the device, and the computer 30 is one of a plurality of computers connected to the transmission line 12. A pulse transformer 15 is connected to the transmission line 12 in order to achieve electrical insulation for data transmission and reception, and a transmission/reception circuit 13 is connected via this pulse transformer 15. A central processing unit 14 is connected to this transmitting/receiving circuit 13. In addition to various storage devices (not shown), this central processing unit 14 is provided with a digital phase synchronization circuit 31 having a configuration similar to that shown in FIG. Connect the RESET terminal of counter 33.
This synchronization command counter 33 outputs a synchronization data transmission command.
is supplied with a counting clock pulse of a specified period. It is assumed that the synchronization command counter 33 is provided only in this computer 30, for example.

In other words, according to the device configured in this way,
When data is being transmitted to the transmission line 12, that is, when two computers are communicating with each other as a set among a plurality of computers including the computer 30, the data being transmitted to the transmission line 12 is is supplied to the central processing unit 14 via the pulse transformer 15 and the transmitting/receiving circuit 13. As a result, the reception data line 32 is supplied with the transmission data from the transmission line 12, and the sampling clock is synchronized with the reception data by the digital phase synchronization circuit 31. The clock pulses counted by the synchronization command counter 33 continue to be reset as long as there is data on the reception data line 32, that is, the transmission line 12, and no synchronization data transmission command is output.

When no data is transmitted to the transmission line 12, that is, after mutual communication between the computers has temporarily ended, data is no longer supplied to the reception data line 32 of the digital phase synchronization circuit 33 when the communication ends, and at the same time, each The sampling clock of the computer becomes asynchronous. As shown in FIG.
When the count value reaches a predetermined value, the central processing unit 14
Outputs a synchronous data transmission command to.

In this way, if the transmission line 12 is not used for a certain period of time Ta or more, the central processing unit 14 uses the synchronous data transmission command, which becomes an interrupt for the computer 30, without specifying the computer at the receiving end, for example, as described above. Data for sampling clock synchronization such as a Sync signal is transmitted to the transmission line 12. Here, the above-mentioned fixed time Ta is set to the maximum permissible time in which the synchronization deviation of the sampling clock can be recovered.

In other words, the sampling clock of each computer,
For example, the synchronization difference that occurs during a certain period of time Ta is
By sending synchronous data such as Sync signal,
Completely restored and resolved.

Therefore, according to the above-mentioned device, if the transmission line 12 is not used for a certain period of time Ta or more, synchronous data is transmitted, and the sampling clocks of all computers connected to the transmission line 12 are significantly reduced. This makes it possible to maintain constant synchronization at all times without causing significant synchronization deviations.

As described above, according to this invention, in a computer system in which multiple computers are connected in parallel to one transmission line and the computers are synchronized by their respective sampling clocks, data is not transmitted through the transmission line. a synchronization command counter that counts up after a preset time has elapsed from the time when the sampling clock reaches zero, and a synchronization circuit that synchronizes the sampling clock based on synchronization data transmitted to the transmission line according to a command from the synchronization command counter. With this, it is possible to always synchronize a plurality of computers connected to the transmission line. Therefore, without using the transmission line for a long time, it is possible to eliminate the synchronization deviation caused by free running of the sampling clock of each computer, and there is no need to send a synchronization Sync signal every time data is transmitted.
Transmission data can always be reliably sampled at the receiving end. This makes it possible to increase the data transmission speed between each computer,
Reliability in the multi-drop communication system can be sufficiently improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the multi-drop communication method, FIG. 2 is a diagram explaining various communication codes used as data in the above communication method, FIG. 3 is a diagram explaining the conventional transmission data format, and FIG. 4 is a diagram explaining the conventional transmission data format. FIG. 5 is a block diagram explaining a digital phase synchronization circuit, FIG. 5 is a block diagram explaining a data transmission device according to an embodiment of the invention, and FIG. 6 is a diagram explaining the time interval of transmitted data. be. 12...Transmission line, 31...Digital synchronous circuit, 32...Reception data line, 33...Synchronization command counter.

Claims (1)

[Scope of utility model registration request] In a computer system in which multiple computers are connected in parallel to one transmission line and are synchronized by their respective sampling clocks, after a preset time has elapsed since data is no longer transmitted to the transmission line. A data transmission device comprising: a synchronization command counter that counts up; and a synchronization circuit that synchronizes the sampling clock based on synchronization data transmitted to the transmission line according to a command from the synchronization command counter. .