JPH0233238A - Reception clock recovery circuit for start-stop synchronization data - Google Patents

Abstract

PURPOSE:To receive a data of the start-stop synchronization system through the use of a general-purpose LSI capable of sending/receiving a continuous synchronizing system data by providing a means recovering a reception clock from the start-stop synchronization system data. CONSTITUTION:When a reception data RD inputted via an interface circuit 1 is fed to a charge point detection circuit 2, the data is sampled by using a clock pulse CLK from a clock generating circuit 4 and a reproduced reception data RD' is obtained. Simultaneously, the change point detection circuit 2 detects a change point of leading and trailing and a change point detection signal VD is given to a reception 1/n frequency divider circuit 6. The frequency divider 6 resets the CLK by using the VD and applies 1/n frequency division and the pulse subject to 1/n frequency division is fed to the general-purpose LSI 3 as a reception clock RC. Thus, the LSI 3 can receive the start-stop synchronization system data correctly by using the clock RC so as to reproduce the data RD'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data transmission system, and more particularly to a receive clock recovery circuit for asynchronous data.

[Conventional technology]

Generally, continuous synchronization methods and start-stop synchronization methods are known as synchronization methods in digital data transmission systems. In the continuous synchronous method, in addition to data, a clock synchronized with this data is exchanged, but in the asynchronous method,
Only data is sent and received. As is well known,
Start-stop synchronization data has a start bit and a stop bit added before and after a code constituting one character, and is transmitted from the start bit to the stop bit as one frame.

On the other hand, a general-purpose LSI capable of transmitting and receiving continuous synchronous data
There is a general-purpose LSI circuit like this one.

It cannot be used to receive asynchronous data. This is because, as described above, asynchronous synchronization data is only data and does not involve a transmission/reception clock.

[Problem to be solved by the invention]

As described above, the start-stop synchronization data itself is similar to the continuous synchronization data, but unlike the continuous synchronization data, a clock synchronized with the data is not exchanged. Therefore, asynchronous data can be transferred to a general-purpose LSI.
When receiving using.

On the receiving side, the received data must be sampled using the internal clock.

Since the frequency was not guaranteed, there was a drawback that data could be received and reproduced incorrectly. Furthermore, in order to solve the above problem, highly stable oscillators are required on both the receiving and transmitting sides, and the aim is to keep the frequency of slip occurrences as low as possible.

This has the disadvantage that the configuration is extremely complicated and is not economical.

Accordingly, one object of the present invention is to provide a circuit capable of regenerating a received clock from asynchronous data.

[Means to solve the problem]

The reception clock recovery circuit for asynchronous data according to the present invention is a circuit that receives asynchronous data as input data and regenerates a reception clock from the input data.

Clock generating means for generating a clock having a frequency n times the data signal speed of the input data.

Change point detection means for detecting a change point in the input data and generating a change point detection signal.

i? coupled to the clock generating means and the changing point detecting means, and resetting the changing point detection signal; n frequency dividing means for receiving the reset pulse as a signal, dividing the frequency of the clock by n based on the reset pulse, and generating the frequency-divided signal as the received clock.

A non-signal coupled to the n frequency dividing means, detecting that the input data has ended, supplying an input data end signal to the n frequency dividing means, and stopping the n frequency dividing operation of the n frequency dividing means. and detection means.

〔Example〕

Next, nine aspects of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a reception clock recovery circuit for asynchronous data according to an embodiment of the present invention.

The asynchronous data (input data) input through the interface circuit (INF) 1 is processed by the change point detection circuit 2 as a high frequency clock (a frequency n times that of the input data) output from the clock generation circuit (CLKGEN) 4. ) CLK and input to the general-purpose LSI circuit 3.

In addition, the clock CL output from the clock generation circuit 4
K is also input to the reception n frequency divider circuit 6 and the transmission n frequency divider circuit 7. In the change point detection circuit 2.

After sampling the input data (received data),
The changing point of the rising or falling edge of the reproduced received data RD' is detected, and the changing point detection signal VD is outputted to the receiving n frequency divider circuit 6 as a reset pulse. The reception n frequency divider circuit 6 receives the clock signal from the clock generation circuit 4.
The clock signal CLK is frequency-divided by n based on the reset pulse VD from the change point detection circuit 2, and the reception clock RC is sent to the reception clock terminal RXC of the general-purpose LSI circuit 3. For sending n
The frequency dividing circuit 7 receives the clock i4 pulse CLK from the clock generating circuit 4.

The frequency is divided by n and the transmission clock TC is sent to the transmission clock terminal TXC of the general-purpose LSI circuit 3.

In addition, the received data RD' reproduced by the change point detection circuit 2
is input to the reception data input terminal RXC of the general-purpose LSI circuit 3 and the no-signal detection circuit 5. In the no signal detection circuit 5,
When the input reception data RD' becomes no signal for m bits or more, it is assumed that one frame has ended, and the reception n frequency dividing circuit 6 is restarted at the change point of the first data of the next frame. In order to multiply the input data, an input data end signal is supplied to the reception n frequency divider circuit 6, and the n frequency division operation of the reception n frequency divider circuit 6 is stopped.

In FIG. 1, 8.10 is a read-only memory, and 9 is a static random access memory.

11 is a dynamic random access memory.

12 is a dynamic RAM controller, and 13 is a direct memory access (DMA) controller.

4 is a Grogrammag interrupt controller, and 15 is a central processing unit.

Next, the present invention will be described in detail with reference to FIG.

Received data RD input via interface circuit 1
When the signal is supplied to the change point detection circuit 2, it is sampled by the clock pulse CLK from the clock generation circuit 4, and reproduced reception data RD' is obtained. At the same time, the change point detection circuit 2 detects a change point with rising and falling edges, and the change point detection signal VD is sent to the receiving n frequency divider circuit 6.
is input.

In the reception n frequency divider circuit 6, the clock pulse CLK from the clock generation circuit 4 is reset by the reset pulse VD of the change point detection circuit 2, and then divided by n.
General-purpose LSI uses the frequency-divided pulse as the reception clock RC
Supply to 3.

When the no-signal detection circuit 5 detects a continuous no-signal of m or more bits as shown by RDf in FIG. 2 using a clock pulse as shown by RC in FIG. The receiving n frequency dividing circuit 6 is restarted at the point of change of the first data of the first frame sent to the n frequency dividing circuit 6.

By using the method described above, if the byte length of continuous data is limited by taking into account the speed deviation of input data, the input data will not be broken, and the general-purpose LSI circuit 3 can detect changing points. A clock RC that synchronizes the sampled data RD' from circuit 2 with the received data RDK.
I would like to play with it.

Start-stop synchronization data can be received correctly.

〔Effect of the invention〕

As explained above, the present invention includes a change point detection circuit that has the function of sampling received data and detecting the changing points of the rising and falling edges of the reproduced received data, and the clock is adjusted based on the changing points. By providing an n frequency divider circuit with a frequency division function and a no-signal detection circuit that detects the end of data, input data will not be broken when receiving data in general-purpose LSI circuits, and data and clock This has the effect of ensuring the phase relationship.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a reception clock recovery circuit for asynchronous data according to an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the circuit shown in FIG. 1...Interface circuit (INF), 2...
・Changing point detection circuit, 3...General-purpose LSI circuit, 4...
- Clock generation circuit (CLKGEN), 5... No signal detection circuit, 6, 7... Clock n frequency division circuit.

Claims (1)

[Claims] 1. A circuit that receives asynchronous data as input data and regenerates a reception clock from the input data, the circuit generating a clock having a frequency n times the data signal speed of the input data. a clock generating means; a changing point detecting means for detecting a changing point of the input data and generating a changing point detection signal; and a changing point detecting means coupled to the clock generating means and the changing point detecting means to generate a reset pulse for the changing point detection signal. n frequency dividing means for dividing the frequency of the clock by n based on the reset pulse and generating the frequency-divided signal as the received clock; and a no-signal detecting means for detecting the completion of the input data and supplying an input data end signal to the n frequency dividing means to stop the n frequency dividing operation of the n frequency dividing means. Receiving clock recovery circuit for system data.