JP2001285262A - Phase correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase correction device that adjusts a data signal so that no point of change of the data signal appears in the same timing as the read timing of the data signal. SOLUTION: A data signal change point detection means 5 detects the timing of change of the data signal, a clock timing detection means 4 detects the buildup or fall timing of a clock signal, and a phase correction data signal output means 6 compares the point of change of the data signal detected by the data signal change point detection means 5 with the clock timing detected by the clock timing detection means 4 to output the data signal whose phase is corrected, thereby making it possible to read the data signal in matching with the buildup or fall timing of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase correction device in a data transmission apparatus for preventing a data signal change point from appearing at the same timing as a data signal read timing.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional data transmission device. This data transmission device includes a reception data signal transmission unit 12 for transmitting a data signal from a data transmission device 11, a clock signal transmission unit 13 for transmitting a clock signal, and a reception data signal based on the falling or rising timing of the clock signal. Transmission means 12
Receiving means 1 for receiving the received data signal output by
4

In this configuration, when the data transmission device reads the received data signal from the reception data signal transmission means 12, the data reception means 14 monitors the clock signal on the clock signal transmission means 13 and synchronizes with the falling edge of the clock. Then, a data signal is read from the reception data signal transmission means 12.

[0004]

However, in the case of the conventional data transmission apparatus, when the read timing of the data signal and the change point of the data signal coincide with each other due to a delay in data transmission and a propagation delay by a cable, etc. There is a disadvantage that the data signal cannot be read.

FIG. 7 is a timing chart for explaining the operation of the above-mentioned conventional data transmission device. The clock signal on the clock signal transmission means 13, the signal generation timing of the data transmission device 11, the data transmission device 11
2 shows the relationship between the data output timing and the received data signal.

As shown in FIG. 1, the data transmitting apparatus 11 generates transmission data at the rising timing t1 of the clock signal. However, the data transmitting apparatus 11 actually outputs data at the timing t2 due to a delay in data transmission.
Has a phase delayed from the generation timing of transmission data. Also, due to the propagation delay caused by the cable, the received data signal has a further delayed phase, and the data signal cannot be read when the read timing of the data signal coincides with the change point t3 of the data signal.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and it is an object of the present invention to provide a phase correcting apparatus for preventing a data signal change point from appearing at the same timing as a data signal read timing. With the goal.

[0008]

A phase correction device according to the present invention comprises a clock signal transmitting means for transmitting a clock signal;
Clock timing detecting means for detecting falling or rising timing of a clock signal, receiving data signal transmitting means for transmitting data received from a data transmitting device, and detecting a change point of a data signal transmitted by the receiving data signal transmitting means. Data signal change point detection means, and a phase correction data signal output for outputting a data signal whose phase has been corrected by comparing the change point of the data signal detected by the data signal change point detection means with the clock timing detected by the clock timing detection means And a phase correction data signal receiving means for receiving the phase correction data signal output by the phase correction data signal output means at the falling or rising timing of the clock signal.

With this configuration, the phase correction data signal output means compares the change point of the data signal detected by the data signal change point detection means with the clock timing detected by the clock timing detection means, and if the two coincide, the phase is corrected. By outputting the corrected data signal, the data signal can be read at the falling or rising timing of the clock signal.

Further, the phase correction device of the present invention has an arbitrary phase correction means for setting the magnitude of the phase to be changed by the phase correction data signal output means.

With this configuration, the phase delay of the data signal in the phase correction data signal output means can be arbitrarily set by the arbitrary phase correction means.

Also, the phase correction device of the present invention includes a clock signal transmission means for transmitting a clock signal, a clock timing detection means for detecting a falling or rising timing of the clock signal, and a data transmission device for transmitting data received from the data transmission device. Receiving data signal transmitting means, detecting a changing point of a data signal transmitted by the receiving data signal transmitting means, detecting a changing point of the data signal detected by the data signal changing point detecting means and detecting a clock timing. A phase correction clock signal output means for outputting a clock signal whose phase has been corrected by comparing the clock timings detected by the means, and a reception data signal based on the falling or rising timing of the phase correction clock signal output by the phase correction clock signal output means Received data transmitted by the transmission means It has a configuration in which a data receiving means for receiving the items.

With this configuration, the phase correction clock signal having a phase delay with respect to the clock signal is generated, so that even if the data signal read timing and the data change timing match, the phase correction clock signal is used. The data signal can be read reliably.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a phase correction apparatus according to a first embodiment of the present invention. This phase correction device includes a reception data signal transmission unit 2 for transmitting a data signal received from the data transmission device 1, a clock signal transmission unit 3 for transmitting a clock signal,
Clock timing detecting means 4 for detecting the falling or rising timing of the clock signal, data signal changing point detecting means 5 for detecting the changing timing of the received data signal, and changing the timing of the received data signal to the falling or rising timing of the clock signal. Phase correction data signal output means 6 for correcting and outputting the phase of the received data signal so as not to match the phase of the clock signal, and phase correction data signal receiving means 7 for receiving the phase correction data signal at the falling or rising timing of the clock signal. ing.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to the timing chart shown in FIG. In the figure, the clock signal is a signal transmitted by the clock signal transmission means 3, the reception data signal is a signal transmitted by the reception data signal transmission means 2, and the phase correction data signal is a phase correction data signal reception means 7. Is the signal transmitted by

When the change point ta of the data signal detected by the data signal change point detecting means 5 and the clock timing detected by the clock timing detecting means 4 match, the phase correction data signal output means 6 changes the data signal. By shifting the point to the time point tb, the phase correction data signal adjusted so as not to coincide with the clock timing is output to the phase correction data signal receiving means 7.

The phase correction data receiving means 7 reads the phase correction data signal output from the phase correction data signal output means 6 at the falling or rising timing of the clock signal output from the clock signal transmission means 3.

With this configuration, even when the read timing of the data signal and the fall or rise timing of the data signal overlap, the data signal can be read by shifting the phase of the data signal.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a phase correction apparatus according to a second embodiment of the present invention. This phase correction device is provided with an arbitrary phase correction means 8 for enabling the phase difference between the reception data signal and the transmission data signal to be arbitrarily determined in addition to the configuration shown in FIG.

Next, the operation of this embodiment will be described. The received data signal is transmitted by the received data signal transmission means 2. The data signal change point detecting means 5 detects the falling or rising timing of the received data signal and outputs it to the phase correction data signal output means 6.

The clock signal transmitted by the clock signal transmitting means 3 is transmitted to a clock timing detecting means 4.
Detects the falling or rising timing of the clock signal and outputs it to the phase correction data signal output means 6. The arbitrary phase corrector 8 adjusts the falling or rising timing of the received data signal at an arbitrary phase with respect to the falling or rising timing of the clock signal.

The phase correction data signal output means 6 adjusts the transmission data as set by the arbitrary phase correction means 8 and outputs it to the phase correction data signal receiving means 7. The phase correction data receiving means 7 reads the phase correction data signal output from the phase correction data signal output means 6 at the falling or rising timing of the clock signal output from the clock signal transmission means 3.

With this configuration, even when the data signal reading timing and the falling or rising timing of the data signal overlap, the data signal can be read by shifting the phase of the data signal.

(Embodiment 3) FIG. 4 is a block diagram showing a configuration of a phase correction apparatus according to a third embodiment of the present invention. The same components as those in Embodiment 1 are denoted by the same reference numerals. Will be explained.

The phase correction device according to the present embodiment includes a reception data signal transmission means 2 for transmitting a data signal received from a data transmission device 1, a clock signal transmission means 3 for transmitting a clock signal, and a falling edge of a clock signal. Alternatively, a clock timing detecting means 4 for detecting a rising timing, a data signal change point detecting means 5 for detecting a timing of a change of a data signal, and a clock so that a change timing of the clock signal does not coincide with a falling or rising timing of the data signal. And a data receiving means 10 for receiving the received data signal at the falling or rising timing of the phase corrected clock signal.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to the timing chart shown in FIG. In the figure, a clock signal is a signal transmitted by a clock signal transmitting means 3, a phase correction clock signal is a signal received by a phase correction clock signal output means 9, and a reception data signal is a reception data signal transmission means 2. Is the signal output by

When the change point tc of the data signal detected by the data signal change point detecting means 5 and the clock timing detected by the clock timing detecting means 4 match, the phase correction clock signal output means 9 changes the clock signal. The phase correction clock signal adjusted so that the point does not coincide with the change point of the data signal is supplied to the data receiving means
Output to

The data receiving means 10 reads the data signal transmitted by the received data signal transmitting means 2 at the falling or rising timing td of the phase correction clock signal output from the phase correction clock signal output means 9.

With this configuration, even when the data signal reading timing and the falling or rising timing of the data signal overlap, the data signal can be read by shifting the phase of the clock signal.

[0031]

As described above, according to the present invention, by generating a phase correction data signal having a phase delay with respect to a received data signal, the read timing of the received data signal and the change timing of the received data signal can be improved. Even if the values match, it is possible to provide a phase correction device capable of reliably reading the reception data signal by generating a phase correction data signal in which the change timing of the reception data signal is adjusted.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase correction device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of signals according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a phase correction device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a phase correction device according to a third embodiment of the present invention.

FIG. 5 is a timing chart of signals in Embodiment 3 of the present invention.

FIG. 6 is a block diagram showing data transmission of a conventional communication device.

FIG. 7 is a timing chart showing a data transmission delay and a cable propagation delay;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data transmission device 2 reception data signal transmission means 3 clock signal transmission means 4 clock timing detection means 5 data signal change point detection means 6 phase correction data signal output means 7 phase correction data signal reception means 8 arbitrary phase correction means 9 phase correction clock Signal output means 10 Data receiving means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 BB04 BC03 CC01 CC12 DD08 5K029 CC01 DD02 EE06 HH26 5K047 AA05 GG03 GG06 GG24 GG45 MM63

Claims (3)

[Claims] 1. Clock signal transmitting means for transmitting a clock signal, clock timing detecting means for detecting the falling or rising timing of the clock signal, and received data signal transmitting means for transmitting data received from a data transmitting device. A data signal change point detection means for detecting a change point of a data signal transmitted by the reception data signal transmission means; and a change point of the data signal detected by the data signal change point detection means and the clock timing detection means detecting the change point. Phase correction data signal output means for outputting a data signal whose phase has been corrected by comparing clock timings; and receiving the phase correction data signal output by the phase correction data signal output means at the falling or rising timing of the clock signal. Phase correction data signal receiving means, Phase correcting device, characterized in that it comprises. 2. The phase correction apparatus according to claim 1, further comprising an arbitrary phase correction means for setting a magnitude of a phase to be changed by said phase correction data signal output means. 3. Clock signal transmitting means for transmitting a clock signal, clock timing detecting means for detecting falling or rising timing of the clock signal, and received data signal transmitting means for transmitting data received from a data transmitting device. A data signal change point detection means for detecting a change point of a data signal transmitted by the reception data signal transmission means; and a change point of the data signal detected by the data signal change point detection means and the clock timing detection means detecting the change point. A phase correction clock signal output unit that outputs a clock signal whose phase has been corrected by comparing clock timings; and a reception data signal transmission unit that outputs a received data signal according to a falling or rising timing of the phase correction clock signal output by the phase correction clock signal output unit. The received data signal to be transmitted Phase correction apparatus characterized by comprising: a data receiving means for signals, a.