JPH05244134A - Data synchronizing circuit - Google Patents

Abstract

PURPOSE:To provide the data synchronizing circuit which can be applied to an efficient data transmission executed by the smallest number of interface signal lines. CONSTITUTION:Clocks A-D whose phases are different from each other are supplied to latches 11-14, and by a rise of these clocks, receiving data is respectively latched and outputted. These latch outputs are supplied to a phase discriminating part 16, a variation of a value of the latch outputs is respectively monitored in the part 16, and an optimal latch output which follows the variation of the value of the receiving data is discriminated, and a selecting signal is supplied to selecting parts 17, 18. The selecting part 17 selects the optimal latch output, based on the selecting signal, supplies it to a frame phase-locked circuit 2, executes a frame pattern, and the selecting part 18 selects a clock signal of an optimal phase, based on the selecting signal, supplies it to a bit buffer 4, and extracts only data, based on the frame pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device suitable for application to a data synchronizing circuit such as a high-speed data receiving package (board) in an exchange or the like.

[0002]

2. Description of the Related Art In recent years, in data transmission between packages (boards) in an exchange system, for example, 10M
In order to realize high-speed transmission of bps or more, a phase adjustment bit buffer circuit is required in the receiving side package considering the steady phase error between the transmitting package (board) and the receiving package and the line length difference between the packages. , It becomes necessary to transmit bit phase information, frame phase information, etc. in addition to data.

For this reason, generally, a three-wire interface using a data signal, a clock signal, and a frame signal is adopted as an interface signal between the transmission package and the reception package. With such an interface, the receiving side package fetches the data signal, the clock signal, and the frame signal into the bit buffer circuit, and adjusts the bit phase and the frame phase of the data signal with the clock signal and the frame signal.

[0004]

However, in general, a large number of packages are mounted in an exchange system or the like. For example, one package A to another package B, C ... May need to be transmitted. In such a case, if it is realized by the conventional 3-wire interface described above, 3-wire × m interface lines are required, the number of pins required for each interface connector is increased, and the interface efficiency is very poor. There is a problem that the size also becomes large.

The increase in the number of interface lines also increases the number of elements in the high-speed driver and the high-speed receiver on the receiving side when sending these interface signals to the lines. Since the high-speed driver and the high-speed receiver generally consume a large amount of power, there is a problem that the overall power consumption increases.

The present invention has been made in view of the above problems, and an object thereof is to provide a data synchronization circuit applicable to efficient data transmission by the minimum number of interface signal lines. is there.

[0007]

In order to achieve the above object, the present invention has been realized by including the following characteristic means.

That is, the capturing means for capturing and outputting the data and the n (integer of 2 or more) different in phase every 1 / n period of the 1-bit period for each period corresponding to 1 bit of the data. Clock generating means for generating a clock; detecting means for detecting the value of the data at the timing of the n clocks having different phases for the data and outputting n detection signals; Of the detection signal, the change in the value of the detection signal is monitored for each of the detection signals corresponding to the n clocks having different phases, and the optimum change is made according to the value of the data. It is characterized by including any one of the above detection signals and a determination means for determining and outputting the clock thereof, and outputting the optimum detection signal and the clock of the optimum phase which are synchronized with each other.

[0009]

According to the present invention, the data taken in by the taking-in means is detected (sampled) by the detecting means at the timing of n clocks having different phases generated by the clock generating means. , These detection values (sample values) determine and output an optimum detection signal that has been optimally changed in accordance with the value of the data in the determination unit, and a clock of the optimum phase corresponding to this, and output Since the optimum detection signal and the optimum phase clock that are synchronized with each other can be obtained, the number of signal lines to be taken in can be reduced to 1/3 compared to the conventional one, and the data for high-speed data transmission can be reduced. The synchronous circuit can be realized with a simple configuration.

Therefore, the data synchronizing circuit as described above can be applied to the data extraction including the frame synchronizing information inside and the data extraction and the clock generation at the optimum timing synchronized with each other by the self-synchronizing means. The data synchronizing circuit as described above can also be applied as a clock phase synchronizing circuit in the preceding stage of the frame synchronizing circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention applied to a data synchronizing circuit of a data receiving apparatus will be described with reference to the drawings.

An object of this embodiment is to realize a data receiving device which can take in only a data signal in which a frame pattern is inserted from a data transmitting device and efficiently extract data with a synchronous circuit having a simple structure. In order to achieve this purpose, a period T corresponding to 1 bit of received data
A four-phase clock generator that generates clocks with different phases for each 1/4 period, a latch circuit that latches received data with each of these four types of clocks, and the values of these four latch outputs. Each of these changes is monitored, and the optimum latch output that follows the change in the value of the received data and the phase determination unit that determines the clock corresponding to this latch output, and the optimum latch output and the optimum phase The frame pattern is collated from the selector for selecting the clock and the clock of the optimum latch output and the optimum phase to extract the data.

FIG. 1 is a functional block diagram of a data transmitting apparatus and a data receiving apparatus according to this embodiment.

In FIG. 1, the data receiving device 20
Is composed of a clock phase synchronization circuit 1, a frame phase synchronization circuit 2, a clock generator 3, a bit buffer 4, a frequency divider 5, and a high speed receiver 6.

The data transmission device 30 comprises a frame pattern insertion unit 31 and a high speed driver 33.

In the data transmitting device 30, the frame pattern is inserted into the data by the frame pattern inserting section 31 and the data is supplied to the high speed driver 33. High speed driver 33
Transmits this data as transmission data (for example, 10 Mbps) to the high speed receiver 6 of the data receiving device 20.

The clock generator 3 generates a 20 MHz clock signal and supplies it to the four-phase clock generator 15 and the frequency divider 5. A frame pulse FP is also generated and supplied to the bit buffer 4. The frequency divider 5 divides the clock signal of 20 Mbps into 1/2 and supplies it to the bit buffer 4.

The high speed receiver 6 supplies the received data to the latches 11-14. On the other hand, four-phase clock generator 15
Generates clocks A to D having different phases as shown in FIG. 2 from the supplied clock signal of 20 Mbps, clock A is supplied to the latch 14, clock B is supplied to the latch 13, and clock C is supplied. Supply to the latch 12,
The clock D is supplied to the latch 11. The clocks A to D are also supplied to the selection unit 18.

The latch 11 latches the received data supplied from the high-speed receiver 6 at the pulse rising timing of the clock D and selects the latch signal LD from the selection unit 17.
And the phase determination unit 16 are supplied. The latch 12 latches the received data supplied from the high-speed receiver 6 at the pulse rising timing of the clock C and supplies the latch signal LC to the selection unit 17 and the phase determination unit 16. The latch 13 latches the reception data supplied from the high-speed receiver 6 at the pulse rising timing of the clock B, and outputs the latch signal LB to the selection unit 17 and the phase determination unit 1.
6 and supply. The latch 14 latches the received data supplied from the high speed receiver 6 at the pulse rising timing of the clock A and supplies the latch signal LA to the selection unit 17 and the phase determination unit 16.

The phase determination unit 16 takes in the latch signals LA to LD supplied from the latches 11 to 14 and outputs these signals.
The change of 0 and 1 of the type of latch signal is monitored, and for example, 2 is detected from the latch signal of the phase in which the change of “0 → 1” is detected.
The selection signals S1 and S2 for selecting the latch signal and the clock delayed by the phase are output and supplied to the selection units 17 and 18.

For example, in FIG. 2, since the change of "0 → 1" can be first detected in the latch signal LA, the latch signal LC and the clock C delayed by two phases from the latch signal LA are the optimum latch signal. And the selection signals S1 and S2 for selecting the reception clock phase. In this case, the reason why the latch signal and the clock delayed by two phases are selected is that the latch is performed at a stable timing in the approximate center of the bit section of the received data.
This is, for example, in the waveform of the logic 1 of the second bit of the received data in FIG. 2A, near the change point from 0 → 1 or 1 →
This is because, in the vicinity of the change point to 0, the influence of pulse disturbance and the influence of jitter etc. occur, so that the latched signal latched at a stable timing near the center is selected.

The selection signals S1 and S2 are latch signals L.
When selecting A and clock A, (S1, S2) =
(0, 0) is supplied to the selection units 17 and 18. Further, when the latch signal LB and the clock B are selected (S1, S
2) = (1,0) is supplied to the selection units 17 and 18. Further, when selecting the latch signal LC and the clock C, (S1, S2) = (0, 1) is supplied to the selection units 17 and 18. Further, when selecting the latch signal LD and the clock D, (S1, S2) = (1, 1) is selected by the selecting units 17 and 18.
Supply to.

The selection unit 17 selects and outputs one of the optimum latch signals of the latch signals LA to LD in response to the selection signals S1 and S2 supplied from the phase determination unit 16, and outputs the bit buffer 4 and the CRC check unit 22. And the frame pattern detector 21. Further, the selection unit 18 selects and outputs one of the clocks (CK) having the optimum phase from the clocks A to D by the selection signals S1 and S2 supplied from the phase determination unit 16, and outputs the clock (CK) to the bit buffer 4. .

The CRC check unit 22 performs CRC (Cyclic Redundancy Check: Cycl) on the supplied latch signal (data of optimum timing synchronized with the clock of the optimum phase).
icRedundancy Check) Check. For example, a predetermined frame check sequence (FC
S) to check the received frame for errors,
The error frame is subjected to discard control, or the error frame is retransmitted from the transmitting side. Then, information such as an error frame number is supplied to the frame pattern detection unit 21. This CRC check method is not particularly limited, but for example, existing vertical parity (generation polynomial P (x)
= X + X ⁰ . ) And horizontal parity (generator polynomial P
(X) = X ^m + X ⁰ . ), 2 consecutive transmission verification, CR
C-16 (generation polynomial P (x) = X ¹⁶ + X ¹² + X ²
It depends on +1. ) And CRC-CCITT (generator polynomial P
(X) = X ¹⁶ + X ¹² + X ⁵ +1. ) Etc. can also be used.

The frame pattern detector 21 takes in the latch signal at the optimum timing, detects a predetermined frame pattern FP, outputs it, and supplies it to the bit buffer 4. At this time, error frame discard control is performed based on information such as the error frame supplied from the CRC check unit 22.

The bit buffer 4 extracts a frame pulse from the optimum latch signal supplied from the selection unit 17 based on the timing of the frame pattern FP and uses it as a clock and frame pulse FP (R) generated by its own clock generation unit 3. Output synchronized data. The bit buffer 4 is, for example, MSM6903 (2
56-bit elastic store) or the like, and can be realized with a simple circuit configuration. As described above, only the data could be obtained.

FIG. 2 is an operation timing chart (No. 1) of the digital synchronizing circuit according to this embodiment.

In FIG. 2, (A) shows the received data (0, 1, 0), and (B) shows the clock A (0 phase clock) of the output of the 4-phase clock generator 15, (C) shows the clock B (1/4 phase clock) of the output of the 4-phase clock generator 15, and (D) shows the clock C (2/4 phase clock) of the output of the 4-phase clock generator 15. And (E) is a four-phase clock generator 15
The output clock D (3/4 phase clock) is shown, (F) shows the latch output LA of the latch 14, (G) shows the latch output LB of the latch 13, and (H) shows The latch output LC of the latch 12 is shown, and (I) shows the latch output LD of the latch 11.

FIG. 3 is an operation timing chart (No. 2) of the digital synchronizing circuit according to this embodiment.

In FIG. 3, (A) shows the received data (0, 1, 0), (B) shows the clock A of the output of the 4-phase clock generator 15, and (C) shows 4 The clock B output from the phase clock generator 15 is shown.
(D) shows the clock C of the output of the four-phase clock generator 15, (E) shows the clock D of the output of the four-phase clock generator 15, and (F) shows the latch output LA of the latch 14. (G) is the latch output L of the latch 13.
B is shown, and (H) is the latch output LC of the latch 12.
(I) shows the latch output LD of the latch 11. Also in FIG. 3, the change from "0 → 1" is first detected at the timing of the latch signal LA and the clock A, and at the latch signal LC and the clock C delayed by two phases from these signals, It is determined that it represents the latch signal near the stable center (time point) of the waveform.

According to the above embodiment, the received data in which the frame pattern is inserted is fetched, and the clock phase synchronization and the frame phase synchronization are performed to collate the frame pattern at the optimum timing and extract the data. You can Therefore, it is possible to efficiently extract the data by taking in only one type of data as compared with the conventional method. Therefore, even when data is transmitted from one data transmitting device to a plurality of data receiving devices, the signal line Since the number can be reduced and the number of high-speed drivers and high-speed receivers can be reduced, power consumption can be reduced.

In FIG. 1 of the above embodiment, one pulse (0 and 1) of received data is latched by four phase clocks having different phases, but the invention is not limited to this. For example, it may be realized with a two-phase clock or a three-phase clock, or may be realized with a five-phase clock or more.

Further, in the above embodiment, the pulse width of the clock is not limited to the examples shown in FIGS. For example, 2 or more n pieces (eg 4
The pulse width of the clock may be small or large.

Further, in the above-mentioned one embodiment, the NRZ signal (the clock component is imperfectly included and the direct current component is included) is explained as the received data, but the present invention is not limited to this. For example, a code including a clock component or a code including no DC component can be applied.

Further, in the above embodiment, the phase determination section 16 monitors the change of the latch outputs LA to LD from "0 → 1", but the invention is not limited to this. For example, "1 → 0"
It can even be applied to monitor changes in.

Further, in FIG. 2 of the above embodiment,
First, control is performed so that the latch signal LC delayed by two phases and the clock C are selected from the latch signal LA in which the change of “0 → 1” is detected, but the present invention is not limited to this. For example, control may be performed so that the optimum latch signal at the time when the waveform from the center to the latter half of the 1-bit section becomes stable and the clock of the optimum phase corresponding to this optimum latch signal are selected. .

Further, in FIG. 1 of the above embodiment,
As explained in the configuration of the data transmitter and data receiver,
It is not limited to this. Data transmission board (PWB)
And a data receiving board (PWB) are also suitable.

Further, in the above embodiment, the structure of the frame phase synchronizing circuit 2 is not limited to that shown in FIG. For example, CCITT Recommendation G. It can also be realized by the 706 specification or the like.

Further, although the latches 11 to 14 are used in FIG. 1 of the above embodiment, the invention is not limited to this.

Further, in FIG. 1 of the above embodiment,
Although clocks having different phases are generated from the clock from one clock generating unit 3, the present invention is not limited to this. For example, to generate a clock with a desired n phase,
A plurality of corresponding clock generators may be provided.

[0041]

As described above, according to the present invention, the acquisition means, the clock generation means, the detection means, and the determination means are provided, and the optimum detection signal and the optimum detection signal synchronized with each other are optimized. Since the clock of the phase can be obtained, the number of interface lines between the devices can be reduced and power consumption can be reduced as compared with the related art, and a data synchronization circuit for high-speed data reception can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a data receiving apparatus according to an embodiment of the present invention.

FIG. 2 is an operation timing chart (No. 1) of the data receiving apparatus according to the embodiment of the present invention.

FIG. 3 is an operation timing chart (No. 2) of the data receiving apparatus according to the embodiment of the present invention.

[Explanation of symbols]

1 ... Clock phase synchronization circuit, 2 ... Frame phase synchronization circuit, 11-14 ... Latch, 15 ... 4-phase clock generation unit,
16 ... Phase determination unit, 17, 18 ... Selection unit, 20 ... Data receiving device.

Claims (1)

[Claims] 1. A fetching means for fetching and outputting data, and n (integer of 2 or more) different phases every 1 / n period of the 1-bit period for each period corresponding to 1 bit of the data. Clock generating means for generating a clock; detecting means for detecting the value of the data at the timing of n clocks having different phases with respect to the data and outputting n detection signals; The detection signal is taken in, the change in the value of the detection signal is monitored for each of the detection signals corresponding to the n clocks having different phases, and the optimum change is made according to the value of the data. A data synchronization circuit comprising: a detection unit that determines and outputs any detection signal and its clock, and outputs an optimum detection signal and a clock having an optimum phase that are synchronized with each other.