JP3427761B2 - Synchronous circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit, and more particularly to a synchronizing circuit for receiving a data string when transmitting and receiving a data string between a plurality of devices using an asynchronous method which is one of the data string synchronizing methods. Regarding

[0002]

2. Description of the Related Art Conventionally, in this type of synchronizing circuit, a clock generated by dividing a reference clock of each device is used as a clock for synchronizing a data string. Since these clocks operate independently in each device, the data sequence after reception (synchronized data sequence) does not have the same phase between the devices. In some cases, as shown in the timing chart of FIG. 6, the phase difference may become considerably large.

In the timing chart of FIG. 6,
(A) is a reference clock of the device 1, and (b) and (f) are synchronous clocks of the device 1. (C) is a reference clock of the device 2, and (d) and (h) are synchronous clocks of the device 2. (E) shows the received data of the device 1. (G) and (i) show the data after the reception of the device 1 and the device 2, respectively. As is clear from these waveforms (g) and (i), a large phase difference may occur between them. If the phase difference becomes large, for example, when data transmission / reception is continuously performed between devices, redundant bits are generated instead of being continuous between data, and the efficiency of data transmission may deteriorate.

Next, a plurality of (in this case, three) devices 1 are provided.
7 shows a connection diagram in the case where the devices 3 are interconnected and data is mutually transmitted and received. Device 1 to device 2 and device 3
The data of the device 1 is transmitted to each of the above. The data of the device 2 is also transmitted from the device 2 to the device 1 and the device 3, respectively. Similarly, the data of the device 3 is transmitted from the device 3 to the device 1 and the device 2. Similarly for reception, the device 1 receives the data of the device 2 and the data of the device 3 from the device 2 and the device 3, respectively. The device 2 receives data of the device 1 and the device 3 from the device 1 and the device 3, respectively. The device 3 receives data of the device 1 and the device 2 from the device 1 and the device 2, respectively.

FIG. 8 is a timing chart of data transmission between three devices, that is, devices 1 to 3 configured (interconnected) as shown in FIG. (A), (b), (c) and (d) show the synchronization clock of the device 1, the input data, the data after the internal synchronization and the output data, respectively. Also,
(E), (f), (g) and (h) show the synchronization clock of the device 2, the input data, the data after the internal synchronization and the output data, respectively. Further, (i), (j), (k) and (l) respectively indicate the synchronization clock of the device 3, the input data, the data after the internal synchronization and the output data.

First, when the device 1 transmits data, the devices 2 and 3 receive the data. The data information includes
Information about the device to be transmitted next is also included, and the device transmits data accordingly. Here, the device 2 transmits data. The device 2 transmits data 1 clock after the stop bit from the device 1 is recognized. The data output by the device 2 is the data output by the device 1
The device 3 receives. Then, similarly, the device 3 similarly outputs the data, and the devices 1 and 2 receive the data. At this time, the data received by the device 1 from the devices 2 and 3 are not continuous, and redundant bits are generated.

In order to eliminate such inconvenience, in the prior art, the same clock is distributed between the devices as a clock for synchronization, or a timing signal for matching the clock phases is transmitted between the devices. Was there.

[0008]

However, in the conventional synchronous circuit, when the distance between the devices is large, the voltage level (amplitude) of the clock is attenuated or the waveform is distorted.
It was difficult to transmit the clock with the correct phase.

Therefore, an object of the present invention is to provide a synchronizing circuit having a small phase difference by a simple method without requiring the same synchronizing clock and timing signal for the phase matching described above.

[0010]

In order to solve the above problems, the synchronous circuit according to the present invention employs the following characteristic structure.

(1) In a synchronous circuit for generating a synchronous clock for synchronizing a received data string, a first detection for detecting the start position of the received data string at the rising edge of the detection clock.
Of a rising edge or a falling edge of the detection clock, which is controlled by an output circuit and a timing detecting section including a second detecting circuit for detecting the falling edge, and outputs of the first and second detecting circuits of the timing detecting section. And a synchronous clock generator that outputs a synchronous clock closer to the start position detection.

(2) The synchronizing circuit according to (1), wherein a detection clock is directly input to the first and second detection circuits of the timing detection section and via an inverter circuit.

(3) The synchronous clock generating section includes the first and second clock generating circuits and an OR gate connected to an output side of both the clock generating circuits, and the synchronous clock according to the above (1) or (2). circuit.

(4) In a synchronizing circuit for supplying a synchronizing clock to a data synchronizing section to which a received data string is input, a timing detecting section to which the received data string and a clock from a reference clock generating section are input, and the clock. And a synchronous clock generating section to which the operation signal from the timing detecting section is input, wherein the timing detecting section receives the clocks whose phases are mutually inverted.
The detection circuit, and the synchronous clock generation unit receives first and second clock generation circuits to which the operation signals from the first and second detection circuits and the clocks whose phases are mutually inverted are input. A synchronous circuit having an OR gate connected to the outputs of both clock generation circuits and obtaining the synchronous clock from the OR gate.

(5) The synchronizing circuit according to (4), wherein the phase-inverted clock is obtained by using an inverter circuit.

(6) The first and second detection circuits mutually generate stop signals, and when the start position of the received data string is detected, the operation of the partner detection circuit is stopped (1) to (5). ) Either synchronous circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a synchronous circuit of the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a block diagram of a preferred embodiment of the synchronizing circuit of the present invention. The synchronization circuit 10 includes a reference clock generation unit 20, a timing detection unit 30, a synchronization clock generation unit 40, and a data synchronization unit 50. The clock generated by the reference clock generator 20 is input to the timing detector 30 and the synchronous clock generator 40.
The synchronous clock generator 40 uses it as a reference clock for generating a clock, and the timing detector 30 uses it as a detection clock.

The timing detection section 30 has a first detection circuit 31 and a second detection circuit 32. The detection clock is directly input to the first detection circuit 31 together with the received data string. On the other hand, a clock obtained by inverting the detection clock by the inverter 22 is input to the second detection circuit 32 together with the received data string. The timing detection unit 30 detects the start position and the end position of the data string. The first detection circuit 31 detects the start position of the data string at the rising timing of the detection clock. On the other hand, the second detection circuit 32
Detects the start position of the data string at the falling edge of the detection clock. When the first detection circuit 31 detects the start position of the data string, it generates a first stop signal,
The operation of the second detection circuit 32 is stopped until the first detection circuit 31 detects the end position of the data string. Similarly,
When the second detection circuit 32 detects the start position of the data string, a second stop signal is generated, and the first detection circuit 31 is generated until the second detection circuit 32 detects the stop position of the data string.
To stop.

Next, the synchronous clock generator 40 will be described. The synchronous clock generating section 40 has a first clock generating circuit 41, a second clock generating circuit 42, and an OR (logical sum) gate 43 connected to the outputs of both clock generating circuits 41, 42. First clock generation circuit 41
The reference clock from the reference clock generator 20 and the output of the first detection circuit 31 are input to the. On the other hand, the second clock generation circuit 42 receives the clock obtained by inverting the above-described reference clock by the inverter 21 and the output of the second detection circuit 32. The OR gate 43 receives the outputs of these clock generation circuits 41 and 42 and inputs the synchronization clock to the data synchronization unit 50. Therefore, the first clock generation circuit 41 generates a clock synchronized with the rising edge of the reference clock. On the other hand, the second clock generation circuit 42 generates a clock in synchronization with the fall of the reference clock.

The first and second operation signals from the first and second detection circuits 31 and 32 of the timing detection unit 30 are supplied to the first and second clock generation circuits 41 and 42 of the synchronous clock generation unit 40, respectively. When input, the synchronous clock generator 40
Either one of the first and second clock generation circuits 41 and 42 is started to operate. At this time,
The output of the stopped clock generator is L (low)
The level becomes high, and the OR gate 43 passes the output of the circuit which is operating. The output of the synchronous clock generator 40 outputs either the clock synchronized with the rising edge of the reference clock or the clock synchronized with the falling edge thereof.

The data synchronizing section 50 serves to synchronize the received data string with the synchronizing clock generated by the synchronizing clock generating section 40.

Next, FIG. 4 is a block diagram of an example in which a pair of devices using the synchronization circuit 10 shown in FIG. 1, that is, a device 1 and a device 2 are connected in parallel to a data string. The operation timing chart in this case is shown in FIG. 5A and 5B show reference clocks (or detection clocks) of the device 1 and the device 2, respectively. (C) shows received data. (D) and (f) show the synchronous clocks of the device 1 and the device 2, respectively. (E) and (g) show the data after the reception of the device 1 and the device 2, respectively.

Next, using the configuration diagrams of FIGS. 1 and 4 and the timing charts (waveform diagrams) of FIGS. 2, 3 and 5,
The operation of the synchronizing circuit 10 of the present invention will be described.

The received data string is input to the timing detector 30. A start bit is added to the data string at this time as shown in the timing chart of FIG. 2 (in particular, refer to the reception data of FIG. 2B). A stop bit is added to the end position as shown in FIG. The timing detection unit 30 first detects the start bit shown in FIG. 2B from the data string. As a start bit detection method, a method of judging that the data has changed from H (high) level to L (low) level or a method of recognizing the pattern by adding a specific pattern to the beginning of the data There is a method to judge.

In the timing detecting section 30 during the start bit detecting operation, the first detecting circuit 31 and the second detecting circuit 32 are operating at the same time. Since the first detection circuit 31 performs the detection operation at the rising timing of the detection clock, the first detection circuit 31 detects the start position of the data string at each rising edge of the detection clock. Further, since the second detection circuit 32 performs the detection operation at the fall timing of the detection clock, it detects the start position of the data string at each fall of the detection clock. That is, as the operation of the timing detection unit 30,
The detection operation is performed at each change point of the detection clock. At this time, the first detection circuit 31 stops the first clock generation circuit 41 by the first operation signal until the start bit is detected. Since the second detection circuit 32 generates the second operation signal and stops the second clock generation circuit 42, the synchronous clock generation unit 40 stops the operation.

In the example of the timing chart of FIG.
In the device 1, the start bit is detected at the timing of the detection clock (see FIG. 5A), that is, the first detection circuit 31. When the first detection circuit 31 detects the start bit, the first detection signal is controlled to control the second detection circuit 3
The second operation is stopped and the first operation signal is controlled to start the operation of the first clock generation circuit 41.
In the device 2 of FIG. 5, since the start bit is detected at the falling timing of the detection clock, similarly, when the second detection circuit 32 detects the start bit, the second stop signal is controlled to control the first stop signal. The operation of the second detection circuit 31 is stopped and the second operation signal is controlled to start the operation of the second clock generation circuit 42.

The synchronous clock generator 40 starts generating the synchronous clock under the control of the timing detector 30. In the example of the device 1 of FIG. 5, the first operation signal causes the first
The clock generation circuit 41 of FIG. At this time, since the second detection circuit 32 of the timing detection unit 30 is stopped, the second clock generation circuit 41 remains uncontrolled and stopped, and the circuit operating in the synchronous clock generation unit 40 operates in the first clock. Only the generation circuit 41 is provided. Since the second clock generating circuit 42 outputs the L level when the operation is stopped, the OR gate 43 outputs the clock of the first clock generating circuit 41. That is, the synchronous clock generated by the synchronous clock generator 40 is the clock generated by the first clock generating circuit 41.

Similarly, in the example of the device 2 of FIG. 5, the second clock generation circuit 42 operates and the first clock generation circuit 41 is stopped by the second operation signal. Therefore, the synchronous clock generated by the synchronous clock generator 40 is the second
The clock is generated by the clock generation circuit 42. Here, the reference clock of the synchronous clock generator 40 and the detection clock of the timing detector 30 are the same clock. That is, the synchronous clock generated by the synchronous clock generator 40 is generated with reference to the change point of the detection clock at which the timing detector 30 detects the data string. Note that in device 1 of FIG. 5, the synchronous clock is generated in synchronization with the rising edge of the detection clock, and in device 2 the synchronous clock is generated in synchronization with the falling edge of the detection clock.

The synchronization clock generated by the synchronization clock generator 40 is input to the data synchronizer 50 and synchronized with the received data string.

After controlling the operation of the synchronous clock generator 40, the timing detector 30 detects a stop bit as shown in FIGS. 3 (a)-(d). In FIG. 3, (a) is the reference clock from the reference clock generator 20, (b) is the received data, (c) is the synchronous clock from the synchronous clock generator 40, and (d) is the data after reception. Show. The stop bit is detected at the position where the data string is at the H level, but in order to distinguish it from valid data, as an example of detection, the information of the transmission bit length is added to the beginning of the data string. , There is a method of recognizing the H level when the bit length is exceeded as a stop bit.

When the timing detector 30 detects this stop bit, it controls the synchronous clock generator 40 to stop the operation of the synchronous clock (see FIG. 5 (c)).
In the example of the device 1 of FIG. 5, when the first detection circuit 31 detects the stop bit, the operation of the first clock generation circuit 41 is stopped by the first operation signal, and the second stop signal is changed by the first stop signal. The operation of the detection circuit 32 is started.
On the other hand, in the device 2, when the second detection circuit 32 detects the stop bit, the operation of the second clock generation circuit 42 is stopped by the second operation signal and the first detection circuit 31 is stopped by the second stop signal. To start the operation of.

As a result, the timing detector 30 starts the operation of detecting the start bit of the next data string as described above. Hereinafter, the start bit and stop bit detecting operations are repeated.

The configuration and operation of the preferred embodiment of the synchronizing circuit of the present invention has been described above. However, those skilled in the art can easily understand that this is merely an example and various modifications and changes can be made without departing from the gist of the present invention.

[0035]

As can be understood from the above description, according to the synchronous circuit of the present invention, the detection operation of the start position (start bit) of the data string is performed every half cycle of the detection clock,
A sync clock is generated based on the time point when the start position is recognized to synchronize the data string. Therefore, when transmitting and receiving data between multiple devices, the synchronization clock generated between each device is within half a cycle of the reference clock even if the maximum deviation occurs, and the data deviation between devices is half the reference clock. It has a remarkable practical effect that it can be suppressed within the cycle.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of a synchronizing circuit of the present invention.

FIG. 2 is a timing chart showing start bits of the synchronization circuit of FIG.

FIG. 3 is a timing chart showing stop bits of the synchronous circuit of FIG.

FIG. 4 is a device 1 and a device 2 using the synchronization circuit of the present invention.
FIG.

FIG. 5 is a timing chart explaining the operation of the synchronous circuit of the present invention.

FIG. 6 is a timing chart of a conventional synchronizing circuit.

FIG. 7 is a diagram showing a data transmission / reception connection relationship between a plurality of (three) devices.

FIG. 8 is a timing chart illustrating the operation of the conventional device shown in FIG.

[Explanation of symbols]

10 Synchronous circuit 20 Reference clock generator 21, 22 Inverter circuit 30 Timing detector 31 First Detection Circuit 32 Second Detection Circuit 40 Synchronous clock generator 41 First Clock Generation Circuit 42 Second Clock Generation Circuit 43 OR gate 50 Data synchronization section

Claims (6)

(57) [Claims] 1. A synchronous circuit for generating a synchronous clock for synchronizing a received data string, wherein a start position of the received data string is detected and a detection clock rises.
The first detection circuit for detecting at and the second for detecting at the falling edge
And a synchronization clock controlled by outputs of the first and second detection circuits of the timing detection unit, whichever of rising and falling of the detection clock is closer to the start position detection. And a synchronous clock generating unit for outputting the synchronous circuit. 2. The first and second timing detectors
2. The synchronization circuit according to claim 1, wherein the detection clock is directly input to each of the detection circuits and via an inverter circuit. 3. The synchronous clock generator includes first and second synchronous clock generators.
3. The synchronous circuit according to claim 1, further comprising an OR gate connected to an output side of each of the clock generation circuits of 1 and 2. 4. A synchronization circuit for supplying a synchronization clock to a data synchronization unit to which a received data string is input, comprising: a timing detection unit to which the received data string and a clock from a reference clock generation unit are input; A synchronous clock generation unit to which an operation signal from the timing detection unit is input, the timing detection unit having first and second detection circuits to which the clocks whose phases are mutually inverted are input, The synchronous clock generation unit is connected to the first and second clock generation circuits to which the operation signals from the first and second detection circuits and the clock whose phase is inverted from each other are input, and outputs of the both clock generation circuits. Has an OR gate
A synchronous circuit, wherein the synchronous clock is obtained from the OR gate. 5. The synchronizing circuit according to claim 4, wherein the phase-inverted clock is obtained by using an inverter circuit. 6. The first and second detection circuits mutually generate stop signals, and when the start position of the received data sequence is detected, the operation of the partner detection circuit is stopped. 6. The synchronous circuit according to any one of 5 to 5.