KR20000008814A - Phase synchronization device and method thereof - Google Patents

Abstract

PURPOSE: A phase synchronization device simply synchronizes two signals having a different synchronization. CONSTITUTION: A phase synchronization device includes a data delay part(10) for delaying a long distance clock signal with different N predetermined times, and outputs an input data by responding to each of the long distance clock signal and the delayed signal. A selection signal generator(12) logically assembles the shortest delayed signal with the long-distance clock signal among the delayed signals. A data selector(14) is enabled by answering to the local clock signal, and selectively outputs one among many data of (N+1) generated from the data delay part. A data output part(16) synchronizes an output data of the data selector to the local clock signal, and then outputs the synchronized output data. Accordingly, without an expensive PLL or a complicated circuit, a local clock signal is easily synchronized to the long distance clock signal by using many gates.

Description

Phase synchronizer and method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization device, and more particularly, to a phase synchronization device and method capable of simply synchronizing two out of synchronization signals.

In transmitting and receiving data between the transmitting end and the receiving end, a clock signal (hereinafter referred to as a remote clock signal) transmitted from the transmitting end to the receiving end and a clock signal used when processing the data transmitted from the transmitting end (hereinafter referred to as a local clock signal) When the synchronization between the (local clock)] does not match, the data transmitted from the transmitter and synchronized with the remote clock signal (hereinafter referred to as input data) should be converted into data synchronized with the local clock signal of the receiver.

To this end, conventionally, a phase locked loop (PLL) is used to synchronize the phase of the remote clock signal with the local clock signal. In this case, the phase locked loop has an advantage of tracking the frequency difference between the remote clock signal and the local clock signal. However, a phase locked loop composed of a phase detector, a loop filter and a voltage controlled oscillator or a numerical controlled oscillator has a problem in that it is difficult to design, complex in structure, and expensive.

Thus, conventional phase synchronizers for synchronizing the phases of a remote clock signal and a local clock signal without using the above-described phase locked loop, US patent number disclosed on May 2, 1995 under the heading "Adaptive data seperator". US5412698 and US patent number US5467464, published on November 14, 1995 under the heading "Adaptive clock skew and Duty cycle compensation". However, the phase lock devices shown in these US patents have the problem of being very complicated instead of using a phase lock loop.

SUMMARY OF THE INVENTION The present invention provides a remote clock signal synchronized with the data in a system for receiving data and a remote clock signal transmitted in packet units rather than continuously, and processing the received data using a local clock signal. It is to provide a phase synchronization device that can easily synchronize the local clock signal.

Another object of the present invention is to provide a phase synchronization method performed in the phase synchronization device.

1 is a block diagram of a phase synchronization device according to the present invention.

FIG. 2 is a circuit diagram of one preferred embodiment of the present invention of the apparatus shown in FIG. 1.

3 (a) to 3 (i) are waveform diagrams of respective parts shown in FIG.

4 is a flowchart for explaining a phase synchronization method according to the present invention performed in the apparatus shown in FIG.

In order to achieve the above object, a phase synchronization device according to the present invention for a system for receiving input data and a remote clock signal transmitted in packet units and synchronized with each other, and processing the input data in response to a local clock signal, A data delay means for delaying a clock signal at different N predetermined times and outputting the input data in response to each of the remote clock signal and the delayed signals, a signal delayed for the shortest time of the delayed signals, and A selection signal generating means for logically combining the remote clock signal and outputting the logical combination result as a selection signal, and one of N + 1 data which is enabled in response to the local clock signal and output from the data delay means; Data selection means for selectively outputting in response to the selection signal; It is preferable that the data output means is configured to output data in synchronization with the local clock signal.

In order to achieve the above object, the phase synchronization method according to the present invention is performed in a system for receiving input data and a remote clock signal transmitted in a packet unit and synchronized with each other, and processing the input data in response to a local clock signal. Delaying the input data by T (where T is a period of the remote clock signal) / 4, T / 2, and 3T / 4, and first and second quarters of one period of the remote clock signal; Determining, in which of the third and fourth sections, the level of the local clock signal is transitioned and an input delayed by MT / 4 (where M is 0, 1, 2 or 3) according to the determined section And synchronizing data with the local clock signal, wherein the remote clock signal is input in the order of the fourth, third, second, and first intervals.

Hereinafter, the configuration and operation of the phase synchronization device according to the present invention will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram of a phase synchronization device according to the present invention, which is composed of a data delay unit 10, a selection signal generator 12, a data selector 14, and a data output unit 16. As shown in Figs.

First, in the apparatus shown in FIG. 1, the input data DATAI and the remote clock signal CKR synchronized with each other are transmitted from the transmitter (not shown) to the receiver (not shown) in packet units rather than continuously, and the input data DATA1. ) Is processed by the receiver (not shown) in response to the local clock signal CKL, the phase difference between the local clock signal CKL and the remote clock signal CKR within the length of the packet is equal to that of the local clock signal CKL. Only applicable if within the cycle.

Under the above-described assumption, the data delay unit 10 shown in FIG. 1 delays the remote clock signal CKR at different N predetermined times, and compares the signal delayed by the shortest time among the N signals delayed by a predetermined time. The remote clock signal CKR is output to the selection signal generator 12, and the input data DATAI is output to the data selector 14 in response to each of the remote clock signal CKR and the N delayed signals. Thus, non-delayed input data and input data delayed at N different times can be input from the data delay section 10 to the data selector 14.

The selection signal generator 12 inputs and logically combines the signal delayed by the shortest time among the N signals delayed by the data delay unit 10 and the remote clock signal CKR from the data delay unit 10, and performs a logical combination. One result is output to the data selection section 14 as the selection signal S. The data selector 14 is enabled in response to the local clock signal CKL, and selects one of the N + 1 data output from the data delay unit 10 from the select signal generator 12. Selection is made in response to (S), and the selected signal is output to the data output unit 16.

On the other hand, the data output unit 16 outputs the data selected by the data selector 14 as output data DATAO in synchronization with the local clock signal CKL. Here, the receiver (not shown) processes the output data DATAO in response to the local clock signal CKL.

If N = 3, the configuration and operation of the embodiment according to the present invention of the apparatus shown in Figure 1 will be described as follows.

FIG. 2 is a circuit diagram of a preferred embodiment of the device of FIG. 1 according to the present invention, in which a delay section 22 and four flip-flops 36, 38, 40 and 42 constitute a data delay section 20. FIG. Two inverters 52 and 54 and four AND gates 56, 58, 60 and 62 constituting the selection signal generator 50, and four AND gates constituting the data selector 70. 72, 74, 76, and 78, an OR gate 82, a single inverter 80, and a flip-flop 90 that constitutes a data output unit.

The data delay unit 20, the selection signal generator 50, the data selector 70, and the data output unit 90 shown in FIG. 2 are the data delay unit 10 and the selection signal generator shown in FIG. (12), the data selection section 14 and the data output section 16, respectively, perform the same function.

3 (a) to (i) are waveform diagrams of the respective parts shown in FIG. 2, FIG. 3 (a) shows a waveform diagram of input data DATAI, and FIG. 3 (b) shows a remote clock signal CKR. Fig. 3 (c) shows the waveform diagram of the non-delayed input data D0, and Fig. 3 (d) shows the input data delayed by T / 4 (where T is the period of the remote clock signal). FIG. 3 (e) shows a waveform diagram of the data D2 delayed by T / 2, and FIG. 3 (f) shows a waveform diagram of the data D3 delayed by 3T / 4. 3 (g) shows a waveform diagram of the local clock signal CKL, and FIG. 3 (i) shows a waveform diagram of the output data DATAO.

The data delay unit 20 shown in FIG. 2 delays the remote clock signal CKR shown in FIG. 3B by T / 4, T / 2, and 3T / 4, and delays the delayed clock signals in response to the delayed clock signals. It outputs in response to the input data D1, D2 and D3 and the remote clock signal CKR, and outputs the input data D0 shown in FIG. 3 (a) to the data selector 70 without delay. do. At this time, the remote clock signal CKR shown in FIG. 3B and the output signal of the buffer 24, that is, the signal shown in FIG. The output is 50.

To this end, the delay unit 22 delays and outputs the remote clock signal CKR by T / 4, T / 2, and 3T / 4, respectively. That is, the remote clock signal CKR illustrated in FIG. 3B is delayed by T / 4 in the buffer 24 and output to the clock terminal CK and the inverter 54 of the flip-flop 38, respectively. Delayed by T / 2 in buffers 26 and 28 and outputted to clock terminal CK of flip-flop 40, and flipped by delayed by 3T / 4 in buffers 30, 32 and 34. Is output to the clock terminal CK. Here, the delay time of each of the buffers 26, 28, 30, 32, and 34 may be T / 4. At this time, the flip-flop 36 inputs the input data DATAI input to the data input terminal D in response to the remote clock signal CKR input to the clock terminal CK, and the AND gate of the data selector 70. The data is output to 72 as the first data D0 as shown in Fig. 3D. The flip-flop 38 is input to the clock terminal CK and receives the input data DATAI in response to the remote clock signal CKR delayed by T / 4 in the buffer 24 and the AND gate 74 of the data selector 70. ) Is output as the second data D1 as shown in FIG. 3E, and the flip-flop 40 is input to the clock terminal CK and is delayed by T / 2 in the buffers 26 and 28. In response to the clock signal CKR, the input data DATAI is output to the AND gate 76 of the data selector 70 as the third data D2 as shown in FIG. 3 (f). The flip-flop 42 is input through the clock terminal CK, and in response to the remote clock signal CKR delayed by 3T / 4, the input data DATAI is transferred to the AND gate 78 of the data selector 70. It outputs as data D3 as shown in FIG.3 (g). Here, the second, third and fourth data D1, D2 and D3 correspond to the input data DATAI delayed by T / 4, 2T / 4 and 3T / 4, respectively.

As a result, four signals input to the clock terminal CK of each of the flip-flops 36, 38, 40, and 42, that is, the remote clock signal CKR, the output of the buffer 24, and the output of the buffer 28. And the output of the buffer 34 has a rising edge within one period of the input data DATAI, so that the flip-flops 36, 38, 40, and 42 shown in FIG. 2 are input with four different signals. By triggering the data DATAI, three delayed data D1, D2 and D3 and non-delayed data D0 can be produced.

On the other hand, the selection signal generation unit 50 may be configured to generate the remote clock signal CKR shown in FIG. 3 (b) and the non-delayed remote clock signal CKR shown in FIG. The logical combination is performed, and the result of the logical combination is output to the data selection unit 14 as the selection signal S = S0 S1 S2 S3.

To this end, the inverters 52 and 54 constituting the inverting portion of the selection signal generator 50 invert the remote clock signal CKR and the signal delayed by T / 4 and output the inverted signals to the corresponding AND gates. At this time, the AND gate 56 logically multiplies the remote clock signal CKR and the signal delayed by T / 4 inverted by the inverter 54, and the result of the logical multiplication S0 is the AND gate of the data selector 70. 76). The AND gate 58 logically multiplies the remote clock signal CKR with a signal delayed by T / 4, outputs the result of the logical multiplication S1 to the AND gate 78 of the data selector 70, and outputs an AND gate 60. ) Multiplies the remote clock signal inverted by the inverter 52 and the signal delayed by T / 4, and outputs the result of the logical multiplication (S2) to the AND gate 72 of the data selector 70. The AND gate 62 logically multiplies the remote clock signal inverted by the inverter 52 and the signal delayed by T / 4 inverted by the inverter 54, and ORs the result S3 of the AND gate of the data selector 70. Output to (74).

The data selector 70 shown in FIG. 2 is enabled in response to the inverted local clock signal to select one of the data D0, D1, D2, and D3 to select signals S0, S1, S2, and S3. In response to the selected data, and outputs the selected data to the flip-flop 90.

To this end, the AND gate 72 of the data selector 70 receives the local clock signal inverted by the inverter 80, the output S2 of the AND gate 60, and the positive output D0 of the flip-flop 36. The AND result is output to the OR gate 82. The AND gate 74 logically multiplies the local clock signal inverted by the inverter 80, the output S3 of the AND gate 62, and the positive output D1 of the flip-flop 38. 82). The AND gate 76 ANDs the local clock signal inverted by the inverter 80, the AND gate 56 output S0, and the positive output D2 of the flip-flop 40, and ORs 82. ) The AND gate 78 logically multiplies the local clock signal inverted by the inverter 80, the output S1 of the AND gate 58, and the positive output D3 of the flip-flop 42. 82). At this time, the OR gate 82 ORs the outputs of the AND gates 72, 74, 76, and 78, and outputs the result of the OR to the data input terminal D of the flip-flop 90.

As a result, the data selector 70 determines an optimal sampling signal of the receiver for processing the output data DATAO shown in FIG. 3 (i) in response to the local clock signal CKL shown in FIG. 3 (h). In order to do so, only one data is selectively outputted to the data output unit by the above-described method.

Meanwhile, the flip-flop 90 implementing the data output unit inputs the data selected by the data selector 70 through the data input terminal D and clocks the local clock signal CKL shown in FIG. 3 (h). It inputs through the terminal CK, and outputs the positive output Q thereof as the output data DATAO shown in FIG.

Hereinafter, a phase synchronization method according to the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a flowchart illustrating a phase synchronization method according to an embodiment of the present invention performed in the apparatus shown in FIG. 2. Delaying input data DATAI by different times (step 100) and a local clock signal (Steps 102 to 106) for determining the interval at which the level of (CKL) is transitioned and synchronizing the delayed input data D1, D2 or D3 or the non-delayed data D0 with the local clock signal CKL. Matching step (108 to 114).

Referring to FIG. 4, the delay unit 22 shown in FIG. 2 delays the input data DATAI by T / 4, T / 2, and 3T / 4 as described above (step 100). After the 100th step, the selection signal generator 50 and the data selector 70 shown in FIG. 2 divide the period of the remote clock signal CKR into four equal parts. It is determined in which of the second, third and fourth sections T0, T1, T2, and T3 the level of the local clock signal CKL has transitioned (steps 102 to 106). In this case, the flip-flop 90 shown in FIG. 2 is delayed by MT / 4 (where M is 0, 1, 2 or 3) according to the interval determined in steps 102 through 106. Or D3) and the local clock signal CKL are synchronized (steps 108 to 114).

Looking at the steps 102 through 114 of FIG. 4 in detail, after step 100, it is determined whether the level of the local clock signal CKL has transitioned in the first section TO shown in FIG. Step 102). That is, since the remote clock signal CKR is at the "high" logic level and the local clock signal CKL is at the "low" logic level in the first section TO shown in FIG. Only the selection signal SO to be output is at the "high" logic level, and the selection signals S1, S2 and S3 output from the other AND gates 58, 60 and 62 are at the "low" logic level. Therefore, the output of AND gates 72, 74, and 78 is at a "low" logic level, so that the output of OR gate 82 depends only on the output value of AND gate 76. If the level of the local clock signal CKL is transitioned in the first period T0, that is, when the signal of the "high" logic level is input through the inverter 80, the data D2 delayed by 2T / 4, that is, Synchronization between the positive output of the flip-flop 40 and the local clock signal CKL is adjusted using the flip-flop 90 (step 108).

However, if the level of the local clock signal CKL has not transitioned in the first section TO, whether the level of the local clock signal CKL has transitioned in the second section T1 shown in FIG. Determination (step 104). That is, since the remote clock signal CKR is at the "high" logic level and the local clock signal CKL is at the "high" logic level in the second period T1 shown in FIG. Only the selection signal S1 to be output is at the "high" logic level, and the selection signals S0, S2 and S3 output from the other AND gates 56, 60 and 62 are at the "low" logic level. Therefore, the output of AND gates 72, 74, and 76 is at a "low" logic level, so that the output of OR gate 82 depends only on the output value of AND gate 78. If the level of the local clock signal CKL is transitioned in the second period T1, that is, when the signal of the "high" logic level is input through the inverter 80, the data D3 delayed by 3T / 4, that is, Synchronization between the positive output of the flip-flop 42 and the local clock signal CKL is adjusted using the flip-flop 90 (step 110).

However, if the level of the local clock signal CKL has not transitioned in the second section T1, whether the level of the local clock signal CKL has transitioned in the third section T2 shown in FIG. 3C. (Step 106). That is, since the remote clock signal CKR is at the "low" logic level and the local clock signal CKL is at the "high" logic level in the third section T2 shown in FIG. Only the selection signal S2 to be output is at the "high" logic level, and the selection signals S0, S1 and S3 output from the other AND gates 56, 58 and 62 are at the "low" logic level. Therefore, the output of AND gates 74, 76, and 78 is at a "low" logic level, so that the output of OR gate 82 depends only on the output value of AND gate 72. If the level of the local clock signal CKL is transitioned in the third section T2, that is, when the signal of the "high" logic level is input through the inverter 80, the input data D0 which is relatively undelayed, In step 112, the positive output of the flip-flop 36 is synchronized with the local clock signal CKL using the flip-flop 90 (step 112).

However, if the level of the local clock signal CKL is not transitioned in the third section T2, it means that the level of the local clock signal CKL is transitioned in the fourth section T3 shown in FIG. 3C. do. That is, since the remote clock signal CKR and the local clock signal CKL are both " low " logic levels in the fourth section T3 shown in FIG. 3C, the selection signal output from the AND gate 62 Only S3 is at the "high" logic level, and the select signals S0, S1 and S2 output from the other AND gates 56, 58 and 60 are at the "low" logic level. Therefore, the output of the AND gates 72, 76 and 78 is at a "low" logic level, so that the output of the OR gate 82 depends only on the output value of the AND gate 74. Therefore, when a signal of "high" logic level is input through the inverter 80, the synchronization of the data D1 delayed by T / 4, that is, the positive output of the flip-flop 38 and the local clock signal CKL is flipped. Fit using the flop 90 (step 114).

As a result, it can be seen that the data selection unit 70 shown in FIG. 2 selects data as shown in Table 1 by the selection signal S = S0 S1 S2 S3 by the above-described method.

Clock signal Selection signal S = S0 S1 S2 S3 Output of data selector 70 CKR CKRD One 0 1 0 0 0 D2 One One 0 1 0 0 D3 0 One 0 0 1 0 D0 0 0 0 0 0 1 D1

In Table 1, CKRD represents a remote clock signal delayed by T / 4 output from the buffer 24. Therefore, since the data selector 70 selects data by using the edge of the local clock signal CKL, the problem of the setup hold time for the local clock signal CKL can be eliminated.

The above-described phase synchronization device and method according to the present invention receive a clock signal (or a remote clock signal) that is synchronized with each other and a transmission unit for transmitting data to the receiver unit in packet units and a local clock signal asynchronous with the remote clock signal. It can be applied to any system having a receiver for processing the data. In particular, the phase synchronization device and method according to the present invention can be applied to a system in which a protocol of a high speed serial bus such as 'IEEE1394' is used to transmit and receive data at high speed.

As described above, in the phase synchronization device and method according to the present invention, there is a slight difference between the remote clock signal and the local clock signal between the transmitter and the receiver when data is transmitted in a packet form of a constant length rather than being continuously transmitted. However, if the difference is within one cycle of the local clock signal, there is an effect of simply synchronizing the local clock signal with the remote clock signal with only a few dozen gates without an expensive PLL or complicated circuit configuration.

Claims (7)

A phase synchronization device for a system for receiving input data and a remote clock signal transmitted in a packet unit and synchronized with each other, and processing the input data in response to a local clock signal. Data delay means for delaying the remote clock signal at different N predetermined times and outputting the input data in response to each of the remote clock signal and the delayed signals; Selection signal generating means for logically combining the delayed signal and the remote clock signal for the shortest time of the delayed signals, and outputting the logical combination result as a selection signal; Data selection means enabled in response to the local clock signal and selectively outputting one of the N + 1 data output from the data delay means in response to the selection signal; And And data output means for outputting data output from said data selection means in synchronization with said local clock signal. The method of claim 1, wherein the data delay means Delay means for delaying and outputting the remote clock signal by T / 4 (where T is a period of the remote clock signal), T / 2 and 3T / 4, respectively; A first flip-flop for outputting the input data to the data selection means in response to the remote clock signal; A second flip-flop for outputting the input data to the data selection means in response to the remote clock signal delayed by the T / 4; A third flip-flop for outputting the input data to the data selection means in response to the remote clock signal delayed by the T / 2; And A fourth flip-flop for outputting the input data to the data selection means in response to the remote clock signal delayed by 3T / 4; And the delayed signal by T / 4 corresponds to a signal delayed for the shortest time of the delayed signals. The method of claim 2, wherein the selection signal generating means Inverting means for inverting and outputting the signal delayed by T / 4 and the remote clock signal; First logical AND means for ANDing and outputting the remote clock signal inversely delayed by the T / 4 delayed signal; Second logical AND means for ANDing and outputting the remote clock signal and the signal delayed by T / 4; Third logical AND means for ANDing and outputting the inversed remote clock signal and the signal delayed by T / 4; And A fourth logical AND means for ANDing and outputting the inverted far clock signal and the inverted delayed signal by T / 4, Output of said first, said second, said third and said fourth AND product form said select signal. 4. The apparatus of claim 3, wherein said data selection means is Fifth logical AND means for ANDing and outputting the inverted local clock signal, the output of the third AND product, and the positive output of the first flip-flop; A sixth AND function for ANDing and outputting the inverted local clock signal, the output of the fourth AND product, and the positive output of the second flip-flop; A seventh AND function for ANDing and outputting the inverted local clock signal, the output of the first AND product, and the positive output of the third flip-flop; An eighth AND function for ANDing and outputting the inverted local clock signal, the output of the second AND product, and the positive output of the fourth flip-flop; And And a logical sum means for ORing the outputs of the fifth, sixth, seventh and eighth AND products and outputting the result of the OR as the selected data to the data output means. . The method of claim 4, wherein the data output means And a fifth flip-flop for inputting data output from the data selecting means to a data input terminal and inputting the local clock signal to a clock terminal, and the positive output of the fifth flip-flop is output to the output of the data output means. Phase synchronizing device, characterized in that corresponding. A phase synchronization method performed in a system for receiving input data and a remote clock signal transmitted in a packet unit and synchronized with each other, and processing the input data in response to a local clock signal. (a) delaying the input data by T (where T is a period of the remote clock signal) / 4, T / 2 and 3T / 4; (b) determining which of the first, second, third, and fourth intervals of one period of the remote clock signal is divided into four levels; and (c) synchronizing the local clock signal with the input data delayed by MT / 4 (where M is 0, 1, 2 or 3) according to the determined interval, And the remote clock signal is input in the order of the fourth, third, second, and first intervals. The method of claim 6, wherein the steps (b) and (c) After the step (a), it is determined whether the level of the local clock signal has transitioned in the first section, and if it is determined that the transition has occurred in the first section, synchronization of the input data delayed by 2T / 4 and the local clock signal is performed. Aligning; If the level of the local clock signal is not transitioned in the second section if it is not transitioned in the first section, if it is determined that the transition in the second section, input data delayed by 3T / 4 and the local clock signal Aligning the motivation; If the level of the local clock signal has not been transitioned in the second section, it is determined whether it has transitioned in the third section. Fitting step; And If the level of the local clock signal has not transitioned in the third section, determining that the local clock signal has transitioned in the fourth section, and synchronizing the local clock signal with the input data delayed by T / 4. Phase synchronization method characterized in that it comprises a.