JPS62202624A - High speed data reception circuit system - Google Patents

Abstract

PURPOSE:To attain high speed data transfer by forming several kinds of clocks whose phases are deviated from the oscillator source and selecting and using an optimum clock suitable for data fetch depending on the phase relation with a synchronizing signal. CONSTITUTION:An oscillator 1 generates a clock having the same frequency as the data transfer frequency to be sent. A phase adjusting circuit 2 consists of a delay circuit, deviates the phase of the oscillator output and forms two kinds or over of clocks at minimum whose phases are deviated. A flip-flop 3 uses the clock to latch a synchronizing signal SYNC. When any signal is latched, an input is given to an OR gate 4 and a signal S4 is outputted. A register 5 stores which of flip-flops 3a, 3b...3h latches the SYNC at first. Since the relation of the phases between the clock and the SYNC is known by outputs S51, S52...S58 of the register 5, the clock most suited to data fetch is selected by a selector 6 to fetch the data by using the output of the register 5.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data transfer circuit, and particularly relates to a data reception circuit suitable for high-speed data transfer. [Background of the Invention] The RS 232 C serial interface is an asynchronous (Asynchronous) transfer.

Generally, an IC called 8251A from Intel Corporation is used, and data is taken in by counting the clock count at x16 or x16 times the transfer lock. In this method, when data transfer reaches 50 MHz, the required data acquisition clock becomes 800 MHz (X 16 ) and 5.2 GHz (X (54)).
This cannot be achieved with TTL logic.

As a technique in this field, there is a technique described in Japanese Unexamined Patent Publication No. 60-6985.0 [Object of the Invention] An object of the present invention is to prevent locking of one data transfer when receiving high-speed serial transfer data. If reception is not possible, a synchronization signal having a certain phase relationship with the transfer lock is used to select a clock for data acquisition on the receiving side, and this clock is used to receive data.

[Summary of the invention]

In the conventional pace synchronization method, synchronization was achieved using a frequency higher than the data transfer frequency, but as the data transfer speed increases, it becomes difficult to use a frequency one higher.

As a countermeasure to this, several types of clocks with different phases are created from the source oscillation of the oscillator, and depending on the phase relationship between this clock and the synchronization signal, the lock that is optimal for data acquisition is selected and used. This makes it possible to receive data using only a clock with the same frequency as the data transfer frequency.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to FIGS. 1 to 6.

FIG. 1 shows a circuit that uses a 1 synchronization signal 5YNC to set the clock output from an oscillator inside the data receiving circuit to the optimum phase for receiving data to be transferred.

FIG. 2 is a timing chart showing the operation of each part in FIG. 1.

The oscillator 1 shown in FIG. 1 is an oscillator that generates a clock having the same frequency as the transfer frequency of data to be transferred.

The phase adjustment circuit 2 is composed of a delay circuit, and shifts the phase of the oscillator output to create at least two types of clocks whose phases are equally shifted. As a result, without increasing the oscillation frequency, it is possible to achieve the same operation as the one with the Doma wave number raised.0 Note that Figure 1 shows an example where 8 types of this clock are createdT0 In this case The phase relationship of each clock of 821.822. is shown in Figure 2. ...0822 as shown in 828 is S21 delayed by 1/8 period, S23 is 822 delayed by 1/8 period, and the following 824 to 828 are also delayed by 1/8 period. It was delayed.

Note that when changing the number of clocks to be generated, the phase may be delayed by 1/N periods, where the number of clocks is N.

7 Ripfp tube 3 receives synchronization signal 5YNC by clock
As an example, the waveform of 5YNC becomes as shown in Figure 2 is shown.Q In this case, 1 flip-flop 3d first latches 5YNC @Depending on the timing of 5YNC, Aritube 70 Tube 3α, 3
Although it is uncertain which one of b, .

When this 84 is output, register 5 is 851°S3
2. ...Stores the state of 83B. That is, the register 5 stores which of the flip-flops 3α, 3b, . . . , 5h latched 5YNC first.

Then, the output of register 5 ss1.852. ...S5
Since the phase relationship between the clock and 5YNC is known from 8, the selector 6 selects the most suitable clock for data capture based on the output of this register 5, and data is captured. In the case of FIG. 2, S28 is selected.

FIGS. 1 and 2 are examples in which the rising edge of 5YNC coincides with the displacement point of DATA.

In this example, the clock rises almost at the center of the data, so it can be captured in a stable state.In addition, the phase g ◎ Also, it is desirable to apply the period sequentially according to the accuracy of the internal oscillator. Note that at this time, the contents of the register 5 may change, and the selected clock may change. In this case, the period of the clock for taking in data may change or extra pulses may be generated, so consideration must be taken such as interrupting the taking while one synchronization is applied.

In addition, as an example where the rising edge of 5YNC is at a location other than the displacement point of DATA, FIGS.
In this case, the difference between FIG. 3 and FIG. 1 is that A is shifted by 172 clock cycles.
Tsuk signal S2L 822. . . 82B is connected to the selector 6.

Figure 4 shows an example where 5YNC enters the circuit in Figure 6 at the same timing as in Figure 2. At this time, selector 6 selects 824 and outputs it to 86'. A signal whose phase is shifted by 1/2 period from that of 86 is outputted, and by using this signal, the data receiving circuit 7 can receive the DATA signal whose phase is shifted by 1/2 period. . The output of the data receiving circuit 7 at this time is 87.

In this way, by changing the connection of the clock signal to the selector 6 depending on the phase relationship between 5YNC and DATA, it is possible to obtain a clock signal with a phase most suitable for DATA reception.

FIGS. 5 and 6 are examples of creating three types of clocks with different phases.

The phase adjustment circuit 2 in FIG. 5 delays the clock by 1/6 period and inverts the level, and its output waveform is
Figure 311. S12 and 813. ``Looking at this signal, it has a waveform that is shifted by 1/3 period. Further, the phase adjustment circuit 2 may delay by 1/3 period.

Otherwise, the operation is the same as in FIGS. 1 to 4, and DA'f A can be taken in near the center.

〔Effect of the invention〕

According to the present invention, data is received using a clock that has a constant phase relationship with the data sending clock without receiving an external clock for data transfer, and without having an oscillator with a frequency higher than the data transfer frequency inside the data receiving circuit. Since it can be generated inside the circuit, high-speed data transfer can be performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a data receiving section of a high-speed data transfer circuit showing one embodiment of the present invention, FIG. 2 is an operation timing chart of each part of FIG. 1, and FIG. 3 is a circuit diagram of another embodiment of the present invention. 4 is an operation timing chart of each part in FIG. 3, FIG. 5 is a circuit diagram of a data receiving part showing another embodiment, and FIG. 6 is a circuit diagram of each part in FIG. It is an operation timing chart. 1... Oscillator 2... Phase adjustment circuit 3... Flip-flop 4... OR gate 5... Register 6... Selector 7... Data receiving circuit,...

Claims (1)

[Claims] With high-speed serial data transfer, data is continuously transferred from the sending side at a frequency of f_0, and f_1 (f_
In a method in which a synchronization signal having a certain phase relationship with data is transferred at a frequency of 1<<f_0), the receiving side has an oscillator with the same frequency of f_0 as the sending side, and the phase is shifted from this oscillator at regular intervals. It has a phase adjustment circuit that generates several different clocks, and uses these out-of-phase clocks to latch the incoming synchronization signal. A register that stores each state of the flip-flop group at the time the synchronization signal is latched, a selector that selects one clock from among the several types of clocks mentioned above based on this stored state, and a register that synchronizes with the selected clock. 1. A high-speed transfer data receiving circuit system, characterized in that a circuit is provided to sequentially receive transmitted data.