JPH10145350A - Interconnection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the simple interconnection circuit that receives a plurality of input signals by using a same clock, independently of relation of phase lead/ lag and that has provision for reception of a high-speed signal. SOLUTION: A phase comparator circuit 5 provides an output of a phase lead/lag relation between input clocks 2a and 2b and a phase difference. A control circuit 8 controls a variable delay circuit 6 in such a way that a delay by a phase difference is inserted to input data, corresponding to the clock having a phase lead, and no delay is inserted to the data corresponding to the clock with a phase lag. Furthermore, the control circuit 8 controls a selection circuit 7 so as select the clock with a phase lag as an output clock 4. Thus, a flip-flop 9 latches variable delay circuit outputs 13, whose phase is arranged by using an output clock 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interconnection circuit for data transmission in a communication device or the like. In particular, when receiving a plurality of data transmitted through different transmission paths, high-speed data can be received with a simple configuration.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional phase correction circuit disclosed in Japanese Patent Application Laid-Open No. Sho 60-1944, for example, when receiving data having different phases generated by transmitting through different transmission paths. Is shown. In the figure,
9a, 9b, 9c and 9d are flip-flops, 20 is an inverter, 5 is a phase comparison circuit, and 29 is an automatic phase control circuit.

Next, the operation of the phase correction circuit shown in FIG. 9 will be described. The input data 1a and the input data 1b of the two signals are input clocks 2 synchronized with the respective data.
a and 2b. Although the frequencies of the input clock 2a and the input clock 2b are the same, a phase shift occurs between the input clocks 2a and 2b due to the difference in each transmission path. The input data 1a and 1b are first input to the flip-flops 9c and 9d and are latched by the input clocks 2a and 2b corresponding to the respective data. In this case, the input data 1a and 1b are latched by the clock corresponding to the input data.
There is no problem with the latch timing.

Next, in order to align the phases of the two systems of data with reference to the input clock 2b, the phases of the input clock 2a and the input clock 2b are compared, and the latch timing in the next-stage flip-flops 9a and 9b is optimized. Thus, the automatic phase control circuit 29 is controlled. That is, control is performed by the automatic phase control circuit 29 to insert a delay of a half cycle of the clock or to output the output as it is, so that the output 30 of the automatic phase control circuit becomes the optimal latch timing in the flip-flop 9a. You do it.
By doing so, the input data 1a and 1b can be latched by the same clock inverted from the input clock 2b by the inverter 20.

[Problems to be solved by the invention]

In an interconnection circuit using a conventional phase correction circuit as described above, one reference clock is determined, a phase difference with respect to that clock is detected, and delay insertion processing is performed on data other than the reference clock. I was
Therefore, when the data subjected to the delay insertion processing has a phase delay more than the data having the reference clock,
There was a problem that processing could not be performed. In addition, since a delay of half a clock cycle is inserted by comparing clock phases, there is a problem that a phase difference of one clock cycle or more cannot be dealt with.

In data transmission in a device, a plurality of data may be transmitted using individual cables, and a difference in transmission path length such as a cable length used at that time causes variations in phase of received data. May occur. This phase variation can predict how much a phase difference will occur due to error management such as cable length, but it is difficult to predict the advance or delay of the phase between data. Furthermore, when the data transmission speed is increased, a slight difference in cable length easily causes a phase difference of one clock cycle or more. Therefore, it is necessary to provide a simple interconnection circuit for receiving a plurality of pieces of high-speed data in which the phase lead / lag relationship cannot be predicted with the same phase difference.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. The present invention detects a lead / lag relationship of the phase of input data, and inserts an optimum delay amount into input data, thereby obtaining a plurality of data. It is an object of the present invention to provide an interconnection circuit that can accurately receive such data regardless of the phase relationship of input data.

[0008]

An interconnection circuit according to a first aspect of the present invention is an interconnection circuit for inputting a plurality of data, wherein the phase comparison means compares the phases of clocks of respective input data with each other. When the most delayed input data based on the result of the phase comparison by the comparing means is the specific input data, a clock selecting means for selecting a clock of the specific input data as a reference clock; A delay unit for adding a delay so as to have an optimal timing based on the phase comparison result, a plurality of flip-flops for latching the input data with the reference clock, and controlling the clock selection unit and the delay unit And control means for performing the control.

In an interconnection circuit according to a second aspect of the present invention, in an interconnection circuit for inputting a plurality of data, a phase comparison means for comparing phases of clocks of respective input data with each other, and a phase comparison result by the phase comparison means When the most delayed input data is determined as the specific input data, a clock selecting means for selecting a clock of the specific input data as a reference clock, and a first data selecting means for selecting input data other than the specific input data Delay means for adding a delay to the input data from the first data selection means so as to have an optimum timing based on the phase comparison result; and a specific input data or a specific output from the delay means. A plurality of second input data selecting means for selecting one of input data other than data; Wherein the reference clock plurality of second
A plurality of flip-flops for latching each output data from the input data selecting means, a control means for controlling the clock selecting means, the first data selecting means, the delay means, and the second input data selecting means; And one of the second selecting means selects the specific input data, and the second selecting means other than the second selecting means selects the input data from the delaying means.

[0010] An interconnection circuit according to a third aspect of the present invention is an interconnection circuit for inputting a plurality of data, wherein the interconnection circuit receives a specific input data from a plurality of input data and a clock for the specific input data. Fixed delay means for delaying a maximum possible phase difference between all input data and outputting delayed input data and a reference clock; and a variable delay amount for variably delaying the input data other than the specific input data. Delay means, phase comparison means for comparing the phase of the clock of the input data other than the specific input data with the reference clock, and input data other than the specific input data based on a phase comparison result from the phase comparison means. Control means for controlling the delay amount variable delay means so as to insert a delay with respect to Each input data is obtained by a plurality of flip-flops for latching.

In an interconnection circuit according to a fourth aspect of the present invention, in the interconnection circuit for inputting a plurality of data, a phase comparison means for comparing the phase of a clock of each input data with a reference clock on a receiving side, Means for delaying a total amount of a half cycle of the reference clock and a leading phase for input data having a clock whose phase is ahead of the reference clock based on a phase comparison result of the means; Delay means for delaying a phase obtained by subtracting a delayed phase from a half cycle of the reference clock for input data having a clock delayed in phase from the reference clock; control means for controlling the delay means; And a plurality of flip-flops for latching each output data of the delay means.

In an interconnection circuit according to a fifth aspect of the present invention, in the interconnection circuit for inputting a plurality of data, frame pulse phase comparing means for comparing the phases of frame pulses indicating the beginning of data of each input data; A delay means for delaying data based on the phase comparison result of the phase comparison means, a phase comparison means for comparing the phases of the respective input data with each other, and a clock for latching data based on the phase comparison result Selecting means for performing the above operation, delay means for inserting a delay into data so as to obtain an optimal latch timing when latching with the selected clock, control means for controlling the selecting means and the delay means, and a selected clock. And a plurality of flip-flops for latching each input data delayed by It is intended to receive align the plurality of input data phase.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram of an interconnection circuit according to an embodiment of the present invention, in which signals of two systems of a channel a and a channel b are inputted, and input data 1a and input clock 2a, input data 1b and input clock are input, respectively. 2b, the output data 3a, the output data 3b and the output clock 4 are obtained.

In FIG. 1, reference numeral 5 denotes a phase comparison circuit for comparing the phase difference between the input clock 2a and the input clock 2b;
a and 6b are variable delay circuits for inputting input data 1a and 1b and inserting a delay amount corresponding to a control voltage, and 7 receiving input clocks 2a and 2b and selecting one of them based on a selection control signal. Output selection circuit, 8
Is a control circuit for generating a delay time control voltage for the variable delay circuits 6a and 6b based on the output of the phase comparison result of the phase comparison circuit 5 and for generating a selection control signal for selecting an output signal of the selection circuit 7, 9a and 9b This is a flip-flop that latches the output signal of the variable delay circuit with the output clock 4.

Next, the operation of the interconnection circuit shown in FIG. 1 will be described. The input clock 2a and the input clock 2b are input to the phase comparison circuit 5. Phase comparison circuit 5
Is for comparing the phases of the input clock 2a and the input clock 2b and generating a detection voltage 10 corresponding to the phase difference. That is, a detection voltage 10 corresponding to the amount of phase advance and the amount of phase lag of the input clock 2b with respect to the input clock 2a is generated, and it is detected which of the input clock 2a and the input clock 2b has a phase delay. Can be. From the detection result of the phase comparison circuit 5, the control circuit 8 controls the variable delay circuit 6a,
The variable delay circuits 6a and 6b generate a control voltage that does not provide a delay voltage for the other data.

In the control circuit 8, the selection circuit 7 selects a clock having a phase delay and generates a selection control signal 11 to be output as the output clock 4. Variable delay circuit 6
a, 6b are output from flip-flops 9a,
9b, and the same output clock 4 is input to the flip-flops 9a and 9b.
Input signals a and 9b are latched and output.

Next, the operation of the interconnection circuit shown in FIG. 1 will be described with reference to the timing chart shown in FIG. Input data 1a and input clock 2a are input as channel a, and a transition point of input data 1a appears at the falling edge of input clock 2a. Similarly, input data 1b and input clock 2b are input as channel b, and a transition point of input data 1b appears at the falling edge of input clock 2b. At this time, the input clock 2b has a phase delay of a phase difference φ with respect to the input clock 2a.

The input clock 2a and the input clock 2b are input to a phase comparator 5, which detects a phase delay φ of the input clock 2b and outputs a phase delay φ
Is generated. The control circuit 8 receives the detection voltage 10 generated by the phase comparison circuit 5 and generates a control voltage 12a from the detection voltage 10 to the variable delay circuit 6a to insert a delay of the delay amount φ into the input data 1a. In addition, a control voltage 12b for generating a delay amount of 0 for the variable delay circuit 6b is generated. Further, the control circuit 8 generates a selection control signal 11 such that the selection circuit 7 selects the input clock 2b as the output clock 4.

Thus, the output 13a of the variable delay circuit becomes the input data 1b delayed by φ with respect to the input data 1a.
And the variable delay circuit output 13
b has the same phase as the input data 1b. Further, the control circuit 8 generates a selection control signal 11 such that the output of the selection circuit becomes the input clock 2b, and the output clock 4 becomes a clock having the same phase as the input clock 2b. As a result, the changing points of the variable delay circuits 13a and 13b are both located at the falling edge of the output clock 4. This is the optimal timing when the flip-flops 9a and 9b latch with the output clock 4. Data latched by the same clock at the optimum timing is output as output data 3a, 3b.

On the other hand, the input clock 2a
When there is a phase delay of b with respect to the phase difference b, the detection voltage 10 generated by the phase comparison circuit 5 causes the control circuit 8 to control the variable delay circuit 6a with a control voltage 12 such that the delay amount becomes zero.
a for controlling the variable delay circuit 6b to insert a delay of the delay amount φ into the input data 1b.
Is generated, and the output clock 4
To generate the selection control signal 11 for selecting the input clock 2a. As a result, the output clock 4 becomes a clock having the same phase as the input clock 2a, and the variable delay circuit output 13a and the variable delay circuit output 13b become the optimal timing for latching with the output clock 4.

According to this embodiment, there is an effect that a plurality of input signals can be latched at the optimum latch timing by the same clock regardless of the lead / lag relationship of the phase of the input signal.

It is needless to say that two or more channels can be supported by adding a phase comparison circuit, using a multi-input selection circuit, and controlling the added phase comparison circuit by a control circuit. Absent. In this case, the clock of the input data with the most delayed phase may be used as the reference clock.

Embodiment 2 FIG. FIG. 3 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention. 3, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. 5 is a phase comparison circuit for comparing the phase difference between the input clock 2a and the input clock 2b, 6 is a variable delay circuit for inserting a delay amount corresponding to the control voltage, and 7 is an input of the input clock 2a and the input clock 2b and a selection control signal. 11
A selection circuit 14 for selecting and outputting one of the input data 1a and 1b based on a selection control signal 15 and selecting and outputting one of the input data 1a and 1b based on a selection control signal 15; A selection circuit which inputs data 1a and variable delay circuit output 13 and input data 1b and variable delay circuit output 13 and selects and outputs one of them based on a selection control signal 11, and 8 is based on the phase comparison result of phase comparison circuit 5. A control circuit for generating a control voltage for the variable delay circuit 6 and for generating a selection control signal for selecting an output signal of the selection circuit 7, the selection circuit 14, and the selection circuits 16a and 16b, 9a and 9b are outputs of the variable delay circuit This is a flip-flop that latches a signal with the output clock 4.

Next, the operation of the interconnection circuit shown in FIG. 3 will be described. Based on the result of the phase comparison between the input clock 2a and the input clock 2b by the phase comparison circuit 5, the control circuit 8 generates a control voltage 12 that gives the delay amount of the phase difference to the variable delay circuit 6, and further selects the selection circuit. 14 selects the input data corresponding to the clock having the phase advance and generates a selection control signal 15 to the selection circuit 14 so as to be input to the variable delay circuit 6. Further, the control circuit 8 generates a selection control signal 11 for performing the following control and outputs it to the selection circuit 7, the selection circuit 16a, and the selection circuit 16b. (1) The selection circuit 7 selects a clock with a phase delay. (2) When the selection circuit 16a selects the input data 1a, the selection circuit 14 selects the input data 1b, and the selection circuit 16b selects the input data 1b. The output 13 obtained by delaying the input data 1b selected by the variable delay circuit 6 is selected. When the selection circuit 16b selects the input data 1b, the selection circuit 14 selects the input data 1a,
The selection circuit 16a selects the output 13 obtained by delaying the input data 1a selected by the selection circuit 14 by the variable delay circuit 6.

As a result, the data whose phase is advanced is selected from the result of the phase comparison of the input signal, and the variable delay circuit 6
Thus, the delay amount of the phase difference is inserted, and the clock with the delayed phase is selected and used as the output clock. This is the optimal timing when the flip-flops 9a and 9b latch with the output clock 4. Data latched by the same clock at the optimum timing is output as output data 3a, 3b.

According to this embodiment, a plurality of input signals can be latched at the optimum latch timing by the same clock regardless of the lead / lag relationship of the phase of the input signal, and the effect of reducing the number of variable delay circuits can be obtained.

It is needless to say that two or more channels can be supported by adding a phase comparison circuit, using a multi-input selection circuit, and performing control corresponding to the added phase comparison circuit by a control circuit. Absent. In this case, the clock of the input data with the most delayed phase may be used as the reference clock.

Embodiment 3 FIG. 4 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention. 4, the same reference numerals as those in FIGS. 1 and 3 denote the same or corresponding parts. 17a and 17b are fixed delay circuits for inserting a fixed delay amount φmax, and 5 is an input clock 2
a phase comparison circuit that compares the phase difference between the clock signal a and the input clock 2b with the delay added by the fixed delay circuit 17b; 6, a variable delay circuit that receives the input data 1a and inserts a delay amount corresponding to the control voltage; Reference numeral 8 denotes a control circuit that generates a control voltage for the variable delay circuit 6 based on the phase comparison result of the phase comparison circuit 5, and reference numerals 9a and 9b denote flip-flops that latch the variable delay circuit output 13 and the fixed delay circuit output 18 with the output clock 4, respectively. is there.

Next, the operation of the interconnection circuit shown in FIG. 4 will be described with reference to the timing chart of FIG. The input clock 2a and the input clock 2b are input with a phase difference as shown in FIG. 5, and in the case of FIG. 5, the input clock 2a has a phase lead with respect to the input clock 2b. However, it is assumed that the phase difference is equal to or smaller than φmax in both the case of the phase advance and the case of the phase delay. First, the input clock 2b is input to the fixed delay circuit 17b, and becomes the output clock 4 obtained by adding a delay amount of φmax to the input clock 2b. Here, when the phase comparison circuit 5 compares the phase difference between the input clock 2a and the output clock 4,
As shown in FIG. 5, it is detected that the input clock 2a and the output clock 4 have a phase advance of the input clock 2a by the phase difference φ.

Here, if the input phase difference between the input clock 2a and the input clock 2b is not more than φmax, the input clock 2a is output clock irrespective of the relationship between the advance and delay of the phase of the input clock 2a and the input clock 2b. 4, there is a phase advance. Next, the control circuit 8 controls the variable delay circuit 6 with a control voltage 12 such that a delay corresponding to the phase difference φ detected by the phase comparison circuit 5 is inserted.
And the output 13 of the variable delay circuit changes the input data 1a to φ
Only delayed. Further, the fixed delay circuit 17a
Thus, the fixed delay output data 18 obtained by delaying the input data 1b by φmax is obtained.

As a result, the variable delay circuit output 13 and the fixed delay output data 18 have the same phase, and the change point is located at the falling edge of the output clock 4 which is the output of the fixed delay circuit. This is the optimal timing when the flip-flops 9a and 9b latch with the output clock 4. Data latched by the same clock at the optimum timing is output as output data 3a, 3b.

According to this embodiment, a plurality of input signals can be latched at the optimum latch timing by the same clock regardless of the lead / lag relationship of the phase of the input signal, and the number of variable delay circuits can be reduced and the control circuit can be reduced. There is an effect that control can be simplified.

By adding a phase comparison circuit, a control circuit, and a variable delay circuit, it goes without saying that two or more channels can be handled. In this case, the clock of the input data with the most delayed phase may be used as the reference clock.

Embodiment 4 FIG. 6 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention. 1, 3 and 4 indicate the same or corresponding parts. 5a and 5b are input clocks 2a, respectively.
Phase comparing circuit for comparing the phase difference between the input clock 2b and the receiving clock 19,
Is a variable delay circuit that inserts a delay amount corresponding to the control voltage,
8a and 8b are control circuits for generating delay time control voltages for the variable delay circuits 6a and 6b based on the phase comparison results of the phase comparison circuits 5a and 5b, respectively, 20 are inverters, 9a,
9b is the output signal of the variable delay circuit,
This is a flip-flop that latches at 1.

Next, the operation of the interconnection circuit shown in FIG. 6 will be described. The input clock 2a and the receiving clock 19 are input to the phase comparison circuit 5a. The phase comparison circuit 5a compares the phase of the input clock 2a with the phase of the receiving clock 19, and generates a detection voltage 10a corresponding to the amount of phase advance and phase lag of the input clock 2a with respect to the receiving clock 19. The control circuit 8a includes the phase comparison circuit 5
On the basis of the detected voltage 10a, a control voltage 12a for giving an optimum delay amount to the input data 1a by the variable delay circuit 6a is generated.

Similarly, the input clock 2b and the receiving clock 19 are input to the phase comparison circuit 5b, and based on the result of the phase comparison, the control circuit 8b makes the variable delay circuit 6b determine the optimum delay amount for the input data 1b. The control voltage 12b to be applied is generated. Variable delay circuit outputs 13a, 13b
Are input to flip-flops 9a and 9b, respectively. The same inverted receiving clock 21 is input to flip-flops 9a and 9b, and input signals of flip-flops 9a and 9b are latched and output.

Next, the operation of the interconnection circuit shown in FIG. 6 will be described with reference to the timing chart shown in FIG. Input data 1a and input clock 2a are input as channel a, and a transition point of input data 1a is located at the falling edge of input clock 2a. Similarly, input data 1b and input clock 2b are input as channel b, and a transition point of input data 1b is located at the falling edge of input clock 2b. At this time, the input clock 2a has a phase advance of a phase difference φa with respect to the reference reception clock 19, and the input clock 2b has a phase delay of the phase difference φb with respect to the reference reception clock 19.

The input clock 2a and the input clock 2b are input to phase comparators 5a and 5b, respectively.
Input clock 2 for reference receiving clock 19
a and the phase lag φ of the input clock 2b.
b, and generates a detection voltage corresponding to the phase lead amount φa and the phase delay amount φb. The control circuit 8a receives the detection voltage generated by the phase comparison circuit 5a and inserts a delay of (φa + half cycle) into the input data 1a for the variable delay circuit 6a based on the detection voltage 10a indicating the phase advance of φa. Such a control voltage 12a is generated. Further, the control circuit 8b receives a detection voltage 10b indicating the phase delay of φb generated by the phase comparison circuit 5b and, based on the detection voltage 10b, sends a signal to the variable delay circuit 6b (clock half cycle −φ
A control voltage 12b is generated to insert the delay of b) into the input data 1b.

Due to the control voltages generated by the control circuits 8a and 8b, the variable delay circuit outputs 13a and 13b insert delays of (φa + half clock cycle) and (clock half cycle−φb) with respect to the input data 1a and 1b, respectively. Therefore, the variable delay circuits 13a and 13b have the same phase, and the change point is located at the falling edge of the inverted receiving clock 21 obtained by inverting the receiving clock 19 by the inverter 20. This is the optimum timing when the flip-flops 9a and 9b latch the signal with the inverted receiving clock 21. The data latched by the same clock at the optimum timing is output data 3a, 3a.
Output as b.

According to this embodiment, there is an effect that a plurality of input signals can be latched at an optimum latch timing by a clock having the same phase on the receiving side irrespective of the phase relation of the input signals.

It is needless to say that by adding a phase comparison circuit and a control circuit, it is possible to cope with two or more channels.

Embodiment 5 FIG. FIG. 8 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention, in which signals of two systems of channel a and channel b are inputted,
Input data 1a, 1b, input clocks 2a, 2a
b, input frame pulses 22a, 22b indicating the beginning of the data frame every fixed period, and output data 3
a, output data 3b and output clock 4 are obtained.

In FIG. 8, the same reference numerals as those in FIGS. 1, 3, 4, and 6 denote the same or corresponding parts. Reference numeral 23 denotes a phase comparison circuit that compares the phase difference between the input frame pulse 22a and the input frame pulse 22b, and reference numerals 24a and 24b denote shift registers that shift input data by a clock.
5 is a control circuit for controlling the amount of shift operation of the shift registers 24a and 24b based on the phase difference detection result of the phase comparison circuit 23, 6a and 6b are variable delay circuits for inserting a delay amount corresponding to the control voltage, and 7 is an input. A selection circuit 8 which receives the clock 2a and the input clock 2b and selects and outputs one of them based on a selection control signal. A selection circuit 8 generates a control voltage for the variable delay circuits 6a and 6b based on the phase comparison result of the phase comparison circuit 5. And a control circuit for generating a selection control signal for selecting an output signal of the selection circuit 7.

Next, the operation of the interconnection circuit shown in FIG. 8 will be described. First, the input frame pulse 22
The signals a and 22b are input to a phase comparison circuit 23. The phase comparison circuit 23 compares the phases of the input frame pulse 22a and the input frame pulse 22b, and generates a detection voltage 26 corresponding to the phase difference. That is, the input frame pulse 22
A detection voltage 26 corresponding to the phase lead amount or the phase delay amount of the input frame pulse 22b with reference to a is generated.
The detection voltage 26 indicates which of the input frame pulse 22a and the input frame pulse 22b has a phase delay.

The control circuit 25 determines from the detection result of the phase comparison circuit 23 that the shift registers 24a and 24b give the shift amount of the phase difference to the input data corresponding to the frame pulse 22a or 22b having the leading phase. And the shift registers 24a and 24b generate shift control signals 27a and 27b for the other input data. Here, the phase difference between the shift register outputs 28a and 28b can be made within one clock cycle. next,
According to the method shown in the first embodiment, data latched by the same clock in flip-flops 9a and 9b with the phase shift of one clock cycle or less are output as output data 3a and 3b.

According to this embodiment, a plurality of input signals having a phase difference of one clock cycle or more can be latched at the optimum latch timing by the same clock regardless of the phase relationship of the input signals. To play.

It should be noted that it is possible to cope with two or more channels by adding a phase comparison circuit and a shift register, making the selection circuit a multi-input circuit, and performing control corresponding to the added phase comparison circuit by a control circuit. Needless to say.

[0048]

According to the first aspect of the present invention, the phase advance and the phase delay of the input signal are detected, the optimum delay is inserted into each input data, and the clock to be latched can be selected. Irrespective of the phase advance / delay relationship, a plurality of input signals can be latched at the optimal latch timing by the same clock.

According to the second aspect of the present invention, data to be inserted with a delay is selected, so that a plurality of input signals can be optimally latched by the same clock regardless of the lead / lag relationship of the phase of the input signal. There is an effect that latch can be performed and delay means can be reduced.

According to the third aspect of the present invention, a fixed amount of delay is inserted into the reference signal and a variable delay is inserted into the other signals. Regardless, a plurality of input signals can be latched at the optimal latch timing by the same clock, and the effects of reducing the number of variable delay circuits and simplifying the control of the control circuit can be obtained.

According to the fourth aspect of the present invention, since the phase comparison with respect to the clock on the receiving side and the delay inserting means are provided, a plurality of input signals can be transmitted to the same receiving side regardless of the lead / lag relationship of the phase of the input signal. There is an effect that latch can be performed at an optimal latch timing by a clock having a phase.

According to the fifth aspect of the present invention, the phase comparison means for the frame pulse of the input signal and the phase shift means for the input data based on the input clock are provided. This has the effect that a plurality of input signals having a phase difference of one clock cycle or more can be latched at the optimal latch timing by the same clock.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an interconnection circuit showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the interconnection circuit shown in FIG.

FIG. 3 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention.

FIG. 4 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the interconnection circuit shown in FIG.

FIG. 6 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention.

7 is a timing chart showing the operation of the interconnection circuit shown in FIG.

FIG. 8 is a configuration diagram of an interconnection circuit showing another embodiment of the present invention.

FIG. 9 shows a conventional phase correction circuit used when receiving signals having different phases.

[Explanation of symbols]

1 input data, 2 input clocks, 3 output data,
Reference Signs List 4 output clock, 5 phase comparison circuit, 6 variable delay circuit, 7 selection circuit, 8 control circuit, 9 flip-flop, 10 detection voltage, 11 selection control signal, 12 control voltage, 13 variable delay circuit output, 14 selection circuit, 15
Selection control signal, 16 selection circuit, 17 fixed delay circuit,
18 Fixed delay circuit output, 19 Receiver clock, 20
Inverter, 21 inverted receiving clock, 22 input frame pulse, 23 phase comparison circuit, 24 shift register, 25 control circuit, 26 detection voltage, 27 shift control signal, 28 shift register output, 29 automatic phase controller.

Claims (5)

[Claims] In an interconnection circuit for inputting a plurality of data, a phase comparison means for comparing phases of clocks of respective input data with each other, and input data delayed most based on a phase comparison result by the phase comparison means. In the case of the specific input data, a clock selecting means for selecting the clock of the specific input data as a reference clock, and a delay so that an optimum timing is obtained for input data other than the specific input data based on the phase comparison result. An interconnection circuit, comprising: delay means for adding a clock signal; a plurality of flip-flops for latching each of the input data according to the reference clock; and control means for controlling the clock selection means and the delay means. . 2. An interconnection circuit for inputting a plurality of data, wherein a phase comparing means for comparing phases of clocks of respective input data with each other, and input data which is delayed most based on a phase comparison result by the phase comparing means. When the specific input data is used, clock selecting means for selecting a clock of the specific input data as a reference clock, first data selecting means for selecting input data other than the specific input data, and first data selecting means Delay means for adding a delay so that the input data from the delay unit has an optimal timing based on the phase comparison result; and either the specific input data or input data other than the specific data output from the delay means. And a plurality of second input data selecting means for selecting the plurality of second input data by the reference clock. A plurality of flip-flops for latching each output data from the data selection means, and control means for controlling the clock selection means, the first data selection means, the delay means, and the second input data selection means. Wherein one of the second selecting means selects the specific input data, and the second selecting means other than the second selecting means selects input data from the delay means. circuit. 3. An interconnection circuit for inputting a plurality of data, wherein a maximum possible value of all input data with respect to a specific input data and a clock of the specific input data is selected from the plurality of input data. Fixed delay means for delaying the phase difference to output delayed input data and a reference clock; delay variable delay means for variably delaying input data other than the specific input data; Phase comparison means for comparing the phase of the input data clock and the reference clock,
Control means for controlling the delay amount variable delay means so as to insert a delay for input data other than the specific input data based on a phase comparison result from the phase comparison means;
An interconnection circuit comprising: a plurality of flip-flops for latching each input data delayed by the reference clock. 4. An interconnection circuit for inputting a plurality of data, comprising: a phase comparing means for comparing a phase of a clock of each input data with a reference clock on a receiving side; For input data having a clock whose phase is advanced from the reference clock, the total amount of the half cycle of the reference clock and the phase advanced is delayed, and a clock whose phase is delayed from the reference clock is delayed. Delay means for delaying a phase obtained by subtracting a phase delayed from a half cycle of the reference clock for input data having the same; control means for controlling the delay means; and each output data of the delay means by the reference clock. An interconnection circuit comprising a plurality of flip-flops for latching. 5. An interconnection circuit for inputting a plurality of data, wherein a frame pulse phase comparing means for comparing the phases of frame pulses indicating the head of data of each input data with each other, based on a phase comparison result of the phase comparing means. Delay means for delaying the data, and phase comparison means for comparing the phases of the clocks of the input data,
Selecting means for selecting a clock for latching data based on the result of the phase comparison; delay means for inserting a delay into data so as to obtain an optimal latch timing when latching with the selected clock; and Control means for controlling the delay means, and a plurality of flip-flops for latching each input data delayed by a selected clock, receiving a plurality of input data having different phases in phase. Interconnection circuit to perform.