JPH05336064A - Signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To stably transmit data between devices by automatically preventing the rise point of a clock from approaching the change point of input data. CONSTITUTION:A pulse generating circuit 1 generates two different timing pulses B1 and B2 for the acquisition of data A. A flip flop circuit 3 generates a select signal (b) and the signal the inverse of (b) for switching between pulses B1 and B2. AND circuits 6 and 7 and an OR circuit 8 select one of pulses B1 and B2 by these signals (b) and the inverse of (b) to generate a latch pulse Y. A flip flop circuit 2 discriminates whether the change point of data A approaches the timing of data sampling (latch pulse Y) or not; and if it approaches this timing, the output (select signal) (b) of the flip flop circuit 2 is inverted to shift the timing of the pulse Y by a half clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronizing circuit for synchronizing a clock of its own device with input data, and more particularly to a signal synchronizing circuit for a device for obtaining the clock from the timing of a network synchronizer (DCS).

[0002]

2. Description of the Related Art Regarding the conventional operation of a device that obtains timing from DCS, FIG. 4 is a system configuration diagram, FIG. 5 is a phase diagram of clocks in the device of FIG.
Description will be given with reference to the time charts of data and clocks in the apparatus of FIG. 4 shown in FIGS.

Device A 42 and device B 43 are DCS 4
Although the signal processing operation is performed by accurately obtaining clock timings of the same frequency from 1, the mutual phase relationship between the clocks A and B is unknown between the devices.

That is, the A device 42 and the B device 43, which are geographically distant from each other, both obtain timing from the DCS 41, and clock generators 421 and 431 in the respective devices synchronize the clock A and the clock A from the DCS 41. A clock B is created and the clocks A and B are used as a reference. However, even if both the clock A and the clock B have the same frequency, the time difference d between the changing point of the clock A and the changing point of the clock B is unknown. That is, an arbitrary time difference d can be taken between the clocks A and B (see FIG. 5). Since both the A device 42 and the B device 43 operate with the DCS 41 as a reference, the value of the time difference d is normally determined when the A devices 42 and 43 are started up, and changes after the device is started up. do not do.

When data transmission is performed between the two devices as described above, for example, the data A is transmitted from the device A 42 to the device B 43, and the device A transfers the data A to the device B 43.
If it is attempted to catch the rising edge of the clock B, the change point of the data A may coincide with the rising edge of the clock B. Then, in the B device 43,
In the reception of the data A, the same bit is received twice or the bit is skipped, resulting in unstable reception. That is, in FIG. 6A, the rising point of the clock B is distant from the rising point of the clock A, so stable output data B is obtained, but in FIG. 6B, the rising point of the clock B is Since it is extremely close to the rising point of the clock A, the change point of the data A is just caught, and the output data B is unstable.

[0006]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to make the rising point of the own device clock approach the change point of the input data when transmitting data between devices whose clock phase relationships are unknown to each other. It is an object of the present invention to provide a signal synchronizer that automatically adjusts the phase of the clock of its own device to prevent the above, and enables stable data transmission between the devices.

[0007]

The signal synchronizing circuit of the present invention includes a first pulse and a first pulse which are active for a fixed time from a rising point of an input first clock.
Pulse generating circuit for generating a second pulse that is active for a fixed time from the trailing edge of the clock, and a pulse for generating a latch pulse by selecting one of the first and second pulses by controlling a selection signal. The selection circuit, the second clock having the same frequency as the first clock, and the latch pulse are input, and the selection is output when it is detected that the latch pulse is close to the rising point of the second clock. And a latch pulse switching circuit for switching the type of signal.

That is, when the data from the first device is latched in the second device, the signal synchronizing circuit is
By monitoring whether or not the moment of trying to latch the data by the latch pulse is close to the change point of the data, and if so, by shifting the latch timing by half a clock, the unstable data as described above can be obtained. Avoid receiving operations.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and this signal synchronizing circuit is applied to the B device 43 of FIG. 2 and 3 are timing charts for explaining the operation of the embodiment shown in FIG.

In this signal synchronizing circuit, the pulse creating circuit 1 inputs a clock B and creates a pulse B1 synchronized with the rising edge of the clock B and a pulse B2 synchronized with the falling edge (see FIGS. 1 and 2). The AND circuits 6 and 7 and the OR circuit 8 are flip-flop circuits (F
One of these pulses B1 and B2 is selected in accordance with the state of the output b (and inversion b) of the / F) 3 to generate the pulse Y (see FIGS. 1 to 3). Pulse Y is F
It is used to latch the data A supplied to the clock input terminal C of / F5 and input to the data input terminal D of F / F5, and is also connected to the data input terminal D of F / F2. F /
The clock A is connected to the clock input terminal C of F2.
The output terminal Q of the F / F2 is connected to the clock input terminal C of the F / F3 via the delay circuit 4.

In the initial state of this signal synchronizing circuit,
The pulse B2 is selected by the output b of the F / F3.
If the rising edge of the pulse Y is far from the rising edge of the clock A, the pulse Y can stably capture the data A, and therefore there is no problem as it is (not shown). At this time, the output a of the F / F2 is always "L". However, if the rising edge of the pulse Y is unfortunately close to the rising edge of the clock A (see FIG. 3), as described above, a stable output as the data B cannot be obtained.

Therefore, in this circuit, when the F / F2 detects that the pulse Y is active "H" near the rising point of the clock A, the output a of the F / F2 once becomes "H". .. This change is transmitted to the F / F 3 through the delay circuit 4, and the output b of the F / F 3 is inverted. Then, the pulse B2 has been selected as the pulse Y until now, but the pulse B1 is selected, the pulse Y becomes active at the rising edge of the clock B1, and the data A is captured at a point shifted by a half clock. After that, the data B becomes a stable output. The output a of F / F2 is
When F / F3 is reversed, it returns to "L".

[0014]

As described above, in the synchronization stabilizing circuit of the present invention, when data is transmitted between two devices whose clock phase relationships are unknown, the moment when the input data is to be latched by the clock of the device itself is the above-mentioned. The effect that it becomes possible to perform stable data transmission by monitoring whether the change point of the input data is approaching and if both are approaching, shifting the timing of latching the input data by half a clock There is.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram of pulses B1 and B2 in the embodiment.

FIG. 3 is a timing diagram illustrating switching between pulses B1 and B2 in the embodiment.

FIG. 4 is a system configuration diagram including a device to which the signal synchronization circuit of the present invention is applied.

5 is a diagram showing a mutual phase relationship between clocks A and B created by two devices according to the related art in the configuration of FIG.

FIG. 6 is a time chart diagram of data and clocks in the apparatus of FIG. 9A shows the case where the rising points of the clocks A and B are separated, and FIG. 9B shows the case where the rising points of the clocks A and B are close to each other.

[Explanation of symbols]

 1 pulse creation circuit 2, 3, 5 flip-flop circuit (F / F) 4 delay circuit 6, 7 AND circuit 8 OR circuit 41 network synchronization circuit (DCS) 42 A device 43 B device 421, 431 clock creation unit

Claims (1)

[Claims] 1. A pulse for generating a first pulse that is active for a certain period of time from a rising point of an input first clock and a second pulse that is active for a certain period of time from a falling point of the first clock. A creating circuit, a pulse selecting circuit for selecting one of the first and second pulses to generate a latch pulse by controlling a selecting signal, a second clock having a frequency equal to the first clock, and the latch And a latch pulse switching circuit that switches the type of the selection signal to be output when it detects that the latch pulse is approaching the rising point of the second clock. Synchronous circuit.