JPH03203427A - Phase synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To allow an oscillator in a reference clock generating circuit to generate phase synchronizing clocks at a high speed equivalent to the speed of an input signal by generating multi-phase clocks from a reference clock and selecting one of them correspondingly to the phase of an input packet signal. CONSTITUTION:Only the multi-phase clock corresponding to a change point detecting signal (c) is selected by D-FF circuits 211 to 21N and AND circuits 231 to 23N at the timing of turning a start instructing signal (i) to a high level and can be outputted as a phase synchronizing clock (r) through an OR circuit 25. The reference clock (d) to be the reference of the multiphase clocks (e) to (h) can be allowed to correspond equivalent to the speed of the signal (c), i.e., equivalent to the speed of the input signal (a) and the phase synchronizing clocks can be generated at a high speed without increasing the operation speed of the element to be used.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a main transmission device that uses a point-to-multipoint communication format with a plurality of slave transmission devices, in which a packet signal transmitted by each slave transmission device is transmitted. The present invention relates to a phase-synchronized clock generation circuit that generates a clock that is phase-synchronized with each packet signal in order to identify each packet signal.

[Prior Art] In the digital time division multiplex communication system, in order to accurately reproduce the transmitted packet signal on the receiving side, it is necessary to generate a clock used for identifying the packet signal at the receiving point of the receiving side transmission device. .

In addition, in a wiring configuration in which a main transmission device and a group of slave transmission devices are connected by a passive bus type transmission path, the transmission distance between the main transmission device and each slave transmission device is different, so each slave transmission device The reception phase at the main transmission device changes for each packet signal sent out.

This reception phase difference for each packet signal is 1 of the packet signal.
A clock with a different phase is required for each received packet signal.Therefore, each packet signal is preamplified with bits for the time required to generate such a lock. added as a file.

As the preamble becomes longer, the transmission efficiency decreases, while an increase in transmission speed is unavoidable in order to maintain a predetermined transmission efficiency. Therefore, it is required to obtain a phase synchronized clock with a preamble length as short as possible.

FIG. 8 is a block diagram showing a conventional phase-locked clock generation circuit configured using a PLL (phase-locked loop) circuit.

In the figure, an input signal (1) is input to one input terminal of a phase comparator 81, and its phase comparison output signal is input to a voltage controlled oscillator (VCO) 83 via a loop filter 82. The output signal (phase synchronized clock) (U) of the voltage controlled oscillator 83 is fed back to the other input terminal of the phase comparator 81, and its phase is compared with the input signal (1) to eliminate the phase difference. This is a configuration in which the frequency is controlled and extracted as a phase synchronized clock.

On the other hand, there is a method of identifying an input signal without using a phase synchronized clock by preparing in advance a high-speed clock that is several times to more than ten times faster than the input signal and sampling the input signal at multiple points using the high-speed clock.

FIG. 9 is a block diagram showing an identification circuit configured using multi-point sampling.

In the figure, a multi-point sampling circuit 91 performs multi-point sampling of an input packet signal (2) using a clock (y) output from a clock generation circuit 93, and outputs the result as an output signal (Z). It is.

Here, the operation of the identification circuit configured using multi-point sampling will be explained using a time chart of signals of each part shown in FIG.

The human packet signal (X) is composed of a preamble and a data packet. The input packet signal (X)′ is an enlarged view of the input packet signal (X)′, which shows the second half of the first data packet to the
+1) represents the first half of the data packet. The output signal (Z) is the clock (
This is the result of multi-point sampling of the input packet signal (X).

(Problem to be Solved by the Invention) By the way, in the configuration in which the PLL circuit shown in FIG. 8 is used to generate a phase synchronized clock, a voltage controlled oscillator equivalent to the input signal can be used, which leads to an increase in element speed. However, due to the characteristics of the loop filter, the phase error and the phase pull-in speed are contradictory, and it has been difficult to suppress the increase in phase error and establish phase synchronization at high speed. It was not easy to obtain a phase synchronized clock.

In addition, unlike the PLL circuit, in the input packet signal identification method using multi-point sampling, there is no need to match the phase of the phase synchronized clock for each packet signal, and a very short preamble is required to achieve phase synchronization. It is enough. However, in order to perform multi-point sampling, it is necessary to use an oscillator that generates a high-speed clock that is several times to more than ten times faster than the input signal, and to operate each circuit element at high speed, which increases costs. . Furthermore, since there is a limit to the operating speed, it has been difficult to apply this method to very high-speed input signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase synchronized clock generation circuit that can establish phase synchronization at high speed and at low cost in generating a phase synchronized clock used for identifying and reproducing input packet signals.

[Means to solve the problem]

The present invention provides communication between a main transmission device and a plurality of slave transmission devices that are connected via a passive bus-type transmission line and transmit and receive finite-length packet signals using a digital time division multiplex communication method. In the phase-synchronized clock generation circuit of the main transmission device that generates a phase-synchronized clock that is phase-synchronized with the packet signal transmitted from the transmission device, there is a start circuit that instructs the start of reception of the packet signal, and changes in the rising or falling edge of the packet signal. A change point detection circuit that detects a point, a reference clock generation circuit that generates a predetermined reference clock, a multiphase clock generation circuit that generates multiphase clocks with different phases from the reference clock, and a change point detection circuit that generates a predetermined reference clock. Accordingly, the clock selection circuit compares the phase of the change point with each phase of the multiphase clock and outputs one of the multiphase clocks as a phase synchronized clock.

[For production]

When packet signals transmitted from each slave transmission device to the main transmission device are input with different input phases, a change point detection circuit first detects a change point corresponding to the rising or falling edge of the packet signal. On the other hand, a multiphase clock generation circuit generates a multiphase clock from the reference clock.

In response to the instruction from the start circuit to start receiving packet signals, the clock selection circuit selects one of the multiphase clocks corresponding to the change point of the packet signal, outputs it as a phase synchronized clock, and starts receiving the next packet signal. hold it until

In this way, by generating multiphase clocks from the reference clock and selecting one of them according to the phase of the input packet signal, the oscillator of the reference clock generation circuit can operate at the same speed as the input signal, but at high speed. A phase synchronized clock can be generated.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of a phase synchronized clock generation circuit according to the present invention.

In the figure, a changing point detection circuit 10 detects a changing point of an input packet signal (a), and detects a changing point of a changing point instruction signal (C
) is sent to the clock selection circuit 20. The reference clock generation circuit 30 generates a reference clock (d), and the multiphase clock generation circuit 40 generates multiphase clocks (e), (f), (8), and (b) from this reference clock (d). and sends it to the clock selection circuit 20. The clock selection circuit 20 uses the change point instruction signal (C) to select a multiphase clock (e),
One of (f), (8), and (c) is selected and output as a phase synchronized clock (r). Note that a start instruction signal (i) instructs to start receiving the input packet signal (a).
is output from the start circuit 50, and one of the multiphase clocks selected at that timing is held.

FIG. 2 is a block diagram showing the configuration of one embodiment of the change point detection circuit 10.

In the figure, the change point detection circuit is an exclusive OR (EX-O
R) circuit 11 and a D flip-flop (D-FF) circuit 13. The input packet signal (a) is
It is input to one input part of the EX-OR circuit 11, and its output is taken out as a change point instruction signal (C) and also serves as a clock (CK) for the D-FF circuit 13. D
The output signal of the -FF circuit 13 becomes the D input, and the Q output signal) is input to the other input section of the EX-OR circuit 11.

FIG. 3 is a block diagram showing the configuration of one embodiment of the multiphase clock generation circuit 40. As shown in FIG.

In the figure, the multiphase clock generation circuit includes N delay circuits 41° to 41.degree., each having a different delay time. It outputs N-phase multiphase clocks (e), (f), (g), and (b) from the input reference clock (d).

FIG. 4 is a block diagram showing the configuration of one embodiment of the clock selection circuit 20.

In the figure, the clock selection circuit uses a changing point instruction signal (C
) as D input, and polyphase clocks (e), (f), (chain,
(b) is each clock (CK) input, and the start instruction signal (i) is connected to the enable (EN) terminal D-F
F circuit 21. ~2 IN, D-FF circuit 21°~21
．． an AND circuit 23. to which each of the Q output signals (j), (1), (e) and multiphase clocks (e), (f), (g), (b) are respectively input. ~23N, and the output signals (n), (0), (b), and (q) of each AND circuit 23 and ~23N are logically summed, and the multiphase clock (e) is calculated using the change point instruction signal (C). , (f), (darkness), (b), and outputs a phase synchronized clock (r) obtained by selecting one of them.

5 to 7 are time charts illustrating the operations of the change point detection circuit 10, the multiphase clock generation circuit 40, and the clock selection circuit 20.

The operation of the phase synchronized clock generation circuit of the present invention will be explained below.

First, regarding the operation of the change point detection circuit 10, FIG.
This will be explained with reference to FIGS. 2 and 5.

Note that the signals (a) to (C) shown in FIG. 5 correspond to the signals of each part shown in FIGS. 1 and 2. Further, the first half of the time chart shown here shows a case where the initial state of the Q output signal (b) of the D-FF circuit 13 is at a high level.

In this case, at the first falling point of the input signal (a), the output signal (C) of the EX-OR circuit 11 changes from low level to high level, and the Q output signal (b) of the D-FF circuit 13 changes from low level to high level. ) is inverted to low level, and the output signal (C) of the EX-OR circuit 11 changes from high level to low level.

The time required for this change is determined by the propagation delay time between the element and the wiring, but is faster than the period of the input signal.

Subsequently, at the next rising point of the human input signal (a), EX
- The output signal (C) of the OR circuit 11 changes from low level to high level, and the Q output signal (B) of the D-FF circuit 13 changes from low level to high level.
is inverted to high level, and the output signal (C) of the EX-OR circuit 11 changes from high level to low level. This change is also faster than the period of the input signal, and at the falling point of the next input signal (a), the EX-OR circuit 11
The output signal (C) changes from a low level to a high level, and similarly, an output signal (C) that becomes high level corresponding to the propagation delay time is obtained at each change point of the input signal (a).

Note that even when the initial state of the Q output signal of the D-FF circuit 13 is at a low level, a similar output signal (C) is obtained as shown in the latter half of the time chart of FIG.

Next, the operation of the multiphase clock generation circuit 40 will be explained with reference to FIGS. 1, 3, and 6. In addition, the 6th
Each of the signals (d) to (c) shown in the figure is
Corresponds to the signals of each part shown in the figure.

Each of the delay circuits 41+ to 41M gives a different amount of delay to the reference clock (d) output from the reference clock generation circuit 30, and generates N-phase multiphase clocks (e) and (f).
), (-1 (b) is generated. Note that the case where N=4 is shown here.

Next, the operation of the clock selection circuit 20 will be explained with reference to FIGS. 1, 4, and 7.

Note that the signals (C), (e) to (r) shown in FIG. 7 correspond to the signals of each part shown in FIGS. 1 and 4.

Each D-FF circuit 21 is provided with multiphase clocks (e), (f), (no, (b)) as clock inputs, respectively.
In ゜~2IN, the start instruction signal (i) becomes high level and becomes an enable state, and when the change point detection signal (C) which is the D input is at high level, the clock is activated according to the multiphase clock having a rising point. Only the Q output signal becomes high level. The AND circuit to which the high-level Q output signal is input serves to pass the corresponding multiphase clock. The only multiphase clock selected in this way is outputted as a phase synchronized clock (r) via the OR circuit 25.

In the first half of the time chart shown in FIG. 7, the Q output signal of the D-FF circuit 21.
1) goes from low level to high level.

When the start instruction signal (i) becomes low level, the Q output signal (1) that has become high level is held in that state until the next start instruction signal (i) becomes high level.

In response to the Q output signal (1) that has become high level, the corresponding multiphase clock (g) is output from the AND circuit 233 as an output signal (P), and the phase synchronized clock (r ) is output as

In addition, the Q output signal (1) becomes low level by the start instruction signal (i) shown in the latter half of the time chart, while the Q output signal (g) of the D-FF circuit 21z changes in response to the multiphase clock (f). From low level to high level. Similarly, in the Q output signal (2) which has become high level, the multiphase clock (f) is output from the AND circuit 23! output signal (0)
This is further output as a phase synchronized clock (r).

In this way, the D-FF circuit 21. 21N and the AND circuits 231 to 23N, the change point detection signal (C) is detected at the timing when the start instruction signal (i) becomes high level.
The polyphase clock corresponding to (here, (dirty or (f)
) is the only one selected and can be outputted as a phase synchronized clock (r) via the OR circuit 25. In addition,
As shown in this embodiment, multiphase clocks (e), (f),
The reference clock (d) that is the basis of (80, (b)) is equal to the speed of the change point detection signal (C), that is, the input signal (
It is possible to respond at a speed equivalent to that in a), and furthermore, it is possible to generate a phase synchronized clock at high speed without increasing the operating speed of the elements used.

〔Effect of the invention〕

As described above, in the present invention, a speed equivalent to that of the input signal is sufficient for the oscillator of the reference clock generation circuit, and phase synchronization can be established at high speed without using elements that operate at high speed. That is, the phase synchronized clock generation circuit can be configured with a simple and inexpensive configuration.

Moreover, it becomes easy to shorten the preamble of a packet signal, and transmission efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a phase synchronized clock generation circuit according to the present invention. FIG. 2 is a block diagram showing the configuration of one embodiment of the change point detection circuit. FIG. 3 is a block diagram showing the configuration of an embodiment of a multiphase clock generation circuit. FIG. 4 is a block diagram showing the configuration of an embodiment of the clock selection circuit. FIG. 5 is a time chart explaining the operation of the change point detection circuit. FIG. 6 is a time chart explaining the operation of the multiphase clock generation circuit. FIG. 7 is a time chart explaining the operation of the clock selection circuit. FIG. 8 is a block diagram showing a conventional phase synchronized clock generation circuit configured using a PLL circuit. FIG. 9 is a block diagram showing an identification circuit configured using multi-point sampling. FIG. 10 is a time chart explaining the operation of the identification circuit. 10... Change point detection circuit, 11... Exclusive OR (
EX-OR) circuit, 13...D flip-flop (D
-FF) circuit, 20... clock selection circuit, 21...
- D flip-flop (D-FF) circuit, 23... AND circuit, 25... OR circuit, 30... Reference clock generation circuit, 40... Multiphase clock generation circuit, 41
...Delay circuit, 50...Start circuit. 10 Figure Figure 0 Change point Ten actual output circuit Figure Figure 8 Figure 8

Claims (1)

[Claims] (1) Each slave transmission is performed between one main transmission device and multiple slave transmission devices, which are connected via a passive bus-type transmission path and transmit and receive finite-length packet signals using a digital time division multiplex communication method. A phase synchronized clock generation circuit of the main transmission device that generates a phase synchronized clock that is phase synchronized with the packet signal transmitted from the device includes a start circuit that instructs to start receiving the packet signal, and a start circuit that instructs to start receiving the packet signal; a change point detection circuit that detects a falling change point, a reference clock generation circuit that generates a predetermined reference clock, a multiphase clock generation circuit that generates multiphase clocks with mutually different phases from the reference clock, and the packet signal. a clock selection circuit that compares the phase of the change point with each phase of the multiphase clock and outputs one of the multiphase clocks as the phase synchronized clock in response to a reception start instruction. A phase synchronized clock generation circuit characterized by: