JPH0575206B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a system in which the phase of one of two counters controls the phase of the other counter, and when a phase change occurs in the clocks of both counters, It also relates to a circuit that guarantees stable operation.

(Prior Art) Digital communication devices, such as PCM multiplex converters and synchronous multiplex converters, have circuits that generate various clocks based on a basic clock received from a clock supply device in an exchange. This circuit is composed of various counter systems. Among these, it may be necessary to match the phase of one counter system to the phase of the other counter system so as to always maintain a certain relationship with respect to two counter systems. When the clocks of both systems have the same frequency, this is achieved by applying a control pulse from one to the other and periodically setting the contents of the counter of the other to a specific value.

On the other hand, when performing the same operation with two systems of counters using two types of clocks with different frequencies, for example, after synchronizing the frequencies of both clocks with the PLO circuit, control from one counter is performed. , periodically sets the contents of the other counter to a certain value. This block diagram is shown in FIG. 3, and the time chart is shown in FIG. 4.

In Figure 3, 1 is the counter, 2 is the counter 1
3 is a counter, 4 is a clock input terminal of counter 3, 5 is a control pulse that is output once per period of counter 1, 6 and 7 are D flip-flops, 8 is a 2-input AND gate, 9 is a 8
10 is a load pulse input terminal of the counter 3, and when the pulse arrives here, the contents of the counter 3 change to a specific value.

Here, the clock applied to counter 1 is
CLKA, the clock applied to counter 3 is CLKB.
Assume that CLKB has a longer period than CLKA. Further, it is assumed that the periods of counter 1 and counter 3 are the same.

Now, when the content of counter 1 takes a value C, consider setting the content of counter 3 to a value A' to cause counter 3 to operate in a subordinate manner to counter 1. Assuming that CLKA and CLKB are frequency synchronized but not phase synchronized, CLKB is as shown in the time chart in Figure 4.
There is a possibility that they will take completely different phases, such as CLKB(1) and CLKB(2). Of course, phases other than these two types are also possible, but for the sake of simplicity, we will consider these two types here.

The counter 1 generates a control pulse 5 that goes to the "H" level once in one cycle at a time corresponding to two bits of CLKA. The control pulse 5 is connected to the D input of the D flip-flop 6, and the clock input CK of the D flip-flop 6 is connected to CLKB. Therefore, the Q output of the D flip-flop 6 becomes a control pulse synchronized with the rise of CLKB. This is connected to D flip-flop 7 and 2-input AND
Using a gate, the counter 3 is controlled by a control pulse 9 obtained by extracting one bit width of CLKB from the rising edge of the Q output of the D flip-flop 6. That is, when the control pulse 9 is applied to the load pulse input 10 of the counter 3, the contents of the counter 3 are forced to change to the value A'. The time chart in FIG. 4 shows the contents of the control pulse 9 and counter 3 corresponding to two types of phases of CLKB.
That is, CLKB(1) and 9(1) correspond to counter 3 contents (1), and CLKB(2) and 9(2) correspond to counter 3 contents (2).

In this case, it is assumed that CLKB has a longer period than CLKA, but the circuit format is the same in the opposite case or when CLKA and CLKB have the same period.

(Problem to be Solved by the Invention) However, in the above conventional technology, as can be seen from the time chart in FIG. 4, when the phase of CLKB changes with respect to the phase of CLKA, The time difference t between each rising point of 5
becomes less than the setup time of the D flip-flops 6 and 7, the rising point of the output Q of the D flip-flop 6 becomes unstable, which causes the control pulse 9 to become unstable, that is, the phase of the counter 3 to become unstable. It has the disadvantage that it occurs.

The present invention aims to improve this drawback and provide a stable phase locked circuit.

(Means for Solving the Problems) The present invention is characterized in that it has a plurality of counters each operated by a plurality of clocks which have established frequency synchronization but have not established phase synchronization. In a phase synchronized circuit that determines the phase of another counter in accordance with a phase determination control signal generated based on the contents of a counter, the logic is A phase synchronized circuit has a control signal whose level is inverted, and means for logically manipulating the control signal and the phase determining control signal, and the output of the means is used as a phase determining input of a counter whose phase is determined. .

(Operation) According to the above configuration, while the control signal is at level L, the operation of the phase determination control signal is prohibited. Therefore, if the clock phase fluctuation _tPH is smaller than the width T of the control signal, the circuit operation is stable.

(Example) FIG. 1 is a block diagram of the present invention, and FIG. 2 is a time chart. In Figure 1, 1 to 10 are the third
Same as the figure, 11 is load prohibition pulse, 12 is 2
Input AND gate 13 is the load pulse of counter 3.

Now, at a certain moment, clock CLKB and counter 3
Assume that the content of is in the state shown by subscript (1) in the time chart of FIG. Control signal 11 here
moves back and forth around the content A′ of counter 3.
This signal is at the "L" level for a width T of one bit at CLKB, and is at the "H" level at other times. This width T is set to a value sufficiently larger than the phase fluctuation value of the two clocks CLKA and CLKB determined by the characteristics of the PLO circuit.

At this time, control signals 9(1) and 11(1) are 2 inputs.
The logic is operated by the AND gate 12, and the output signal 13 appears as 9(1) as is, such as 13(1).
This causes counter 3 to have its contents indexed at the next moment.
(2), and at the same time the control signal 11
changes to 11(2). In this state, 2 input AND
Since the signal 11(2) is connected to one input of the gate 12 and the signal 9(1) is connected to the other input, the output signal 13(2) is “L” throughout the entire period of the counter 3. level. In this state, counter 3
Since the signal level at the load pulse input terminal 10 is at the "L" level, the motor is operating at its own self-generated cycle without being forced by an external force. The "cycle that you created yourself" here is the same as the cycle that is forcibly loaded from the outside.

Next, from the state indicated by subscript (2), the clock
Assume that CLKB causes a phase variation of t _PH that is sufficiently small compared to T. At this time, the contents of CLKB, signal 9, and counter 3 are all subscripted in Figure 2.
The waveform changes to the one shown in (3).

In the state indicated by subscript (3), the output 13(3) of the two-input AND gate 12 is still at the "L" level, and the counter 3 is running at the cycle it has created itself without receiving any forced loading from the outside. moving.

In this way, if the state of subscript (1) occurs even once, the contents of the counter 3 are instantaneously and forcibly set to the value A' from the outside, and the state shifts to the state of subscript (2).
In the state of subscript (2), the content of the counter 3 becomes A' at approximately the center of the time width when the control signal 11 is at the "L" level, so the phase fluctuation _tPH of the clock CLKB is more than T. As long as it is small, the operation of the circuit is stable.

In this explanation, regarding the two types of clocks CLKA and CLKB, it is assumed that CLKB has a longer cycle than CLKA, but the circuit configuration will be the same even if the relationship is reversed or if the cycles of both clocks are the same. The circuit configuration is also similar when there are three or more counter systems and one of them controls all the remaining counter systems.

(Effects of the Invention) As explained above, the present invention provides a method of absorbing the clock phase fluctuation width by setting the time width T that is sufficiently larger than the clock phase fluctuation value determined by the characteristics of the PLO circuit. It is becoming. Therefore, it can be easily constructed using general-purpose digital ICs, and its operation is stable. The design of the value of T is
This can be easily done based on the periods of both clocks CLKA and CLKB and the characteristics of the PLO circuit.

This circuit can be used to generate various clocks for use in various digital communication devices, such as PCM multiplex converters and synchronous multiplex converters, based on the basic clock received from the clock supply device. Two systems of counters that operate with two systems of clocks that are synchronized only in frequency and that require mutually maintaining a specific phase relationship can be realized without constructing a complicated phase synchronization circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase-locked circuit according to the present invention, FIG. 2 is a time chart of its operation, FIG. 3 is a conventional phase-locked circuit, and FIG. 4 is a time chart of its operation. 1 is a counter, 2 is a clock input terminal of counter 1, 3 is a counter whose phase is determined by counter 1, 4 is a clock input terminal of counter 3,
5 is a phase determining pulse generated from counter 1, 6
and 7 are D flip-flops, 8 is a 2-input AND gate, 9 is the output of 8, 10 is the phase determining input of counter 3, 11 is the control signal generated from counter 3, 12 is a 2-input AND gate, 13 is the output of counter 3 This is a phase determining pulse.

Claims (1)

[Claims] 1. A phase-determining control signal that includes a plurality of counters each operating on a plurality of clocks with which frequency synchronization is established and phase synchronization is not established, and which is generated based on the contents of one counter. In a phase-locked circuit that determines the phase of another counter according to the above, a control signal provided by the counter whose phase is determined and whose logic level is inverted by a predetermined time width every cycle;
A phase synchronized circuit comprising logic operation means for the control signal and the phase determination control signal, and an output of the means is used as a phase determination input of a counter whose phase is determined. 2. The phase synchronized circuit according to claim 1, wherein the time width is longer than the phase fluctuation of each clock, and the logic operation means is an AND circuit.