JPS6380636A - System and circuit for data transmission - Google Patents

Abstract

PURPOSE:To improve reliability by outputting digital data in synchronism with the leading and trailing edges of a synchronous timing signal and sending digital data in synchronism with a clock which has the same frequency as the maximum frequency of the sent data. CONSTITUTION:An oscillation circuit 2 outputs the sent clock 12 which has the same frequency as the maximum frequency of the sent data. Latch circuits 3 and 4 latch the data sequence with the leading and trailing edges of the sent clock 12 and output the data sequence to a transmission line 13 in order. A received clock 16 is 1/4 period delayed through the operation of a delay circuit 6 and latch circuits 7 and 8 for reception latch the sent data with the leading and trailing edges of the received clock 16. Consequently, the data is securely transmitted without being affected by waveform distortion, etc., in transmission and the frequency of the synchronizing clock is reduced to a half as before to improve the reliability of the data transmission and speed down the operation of a peripheral IC, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system and circuit for transmitting digital data via a communication medium.

[Prior Art] Conventionally, in a digital data transmission system, data is transmitted in synchronization with a clock having a frequency twice as high as the maximum carrier frequency of the data to be transmitted.

Hereinafter, a conventional digital data transmission system will be explained with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram of a conventional digital data transmission circuit. In the figure, 31 is a data supply unit that outputs digital data to be transmitted in synchronization with the output synchronized clock from an oscillation circuit 32, and 32 is necessary for data transmission. 33 is a flip-flop A that latches the transmission data from the data supply unit 31 in synchronization with the rising edge of the transmission clock 41, and 34 is the reception clock signal 4.
The flip-flop B135 that latches the received data sent via the transmission path 37 in synchronization with the second flip-flop B34 is a data processing section that processes the received data received and latched by the flip-flop B34. Note that the left side of the illustrated broken line P is the data transmitting side T, and the right side is the data receiving side R.

Further, 36 is an output data signal from the data supply section 31;
37 is a transmission line, 38 is the transmission side of the transmission line 37, 39
is the receiving side of the transmission line 37, and 40 is the flip-flop B34.
41 is a transmission clock, 42 is a reception clock, both clock signals have a common timing, and 2 of the maximum carrier frequency of transmission data during data transmission.
This is twice the frequency (frequency where one period is the transmission time per one bit of data).

FIG. 4 shows the data transmission timing with the above configuration. Data string to be transmitted, Di, D2°D3. D4.・・・
* is input from the data supply section 31 to the flip-flop 33 via the signal line 36. The flip-flop 33 sequentially latches this data string in synchronization with the rising edge of the transmission clock 41 and outputs it to the transmission line 37. The flip-flop 34 on the receiving side receives the data strings Di, D2 . D3. D4. ... is latched at the rising edge of the reception clock 42 (same timing as the transmission clock 41) and output to the data processing section 35.

[Problems to be Solved by the Invention] However, in the above-mentioned transmission system, when the maximum frequency of data is, for example, 20 MI (z), the transmission clock 41.42 synchronized with the transmission data 39 is 20 MHz x 2 =
40MHz, and such a high-speed clock is transmitted through transmission line 3.
7 must be transmitted. Therefore, the transmission line 37
Depending on the transmission distance or the quality of the transmission line, the waveform of the clock becomes distorted, and the rising and falling waveforms of the clock become dull. As a result, the phase of the transmitted digital data may shift little by little.

If the phase is shifted, the data acquisition timing will be shifted, and there is a possibility that the rising edge of the clock signal may coincide with a change in the output of the transmission data. In such a case, there is a problem that accurate data transmission cannot be performed.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and includes the following configuration as a means for achieving the above-mentioned objects.

That is, a first latch means that latches the digital data to be transmitted at the rising edge of the synchronous timing signal, a second latch means that latches the digital data to be transmitted at the falling edge of the synchronous timing signal, and the second latch means. A selection means is provided for alternately selecting and outputting the output from the means and the output from the first latch means.

[Operation] In the above configuration, digital data is output in synchronization with the rise and fall of the synchronization timing signal, and the digital data is transmitted in synchronization with a clock having the same frequency as the maximum frequency of the transmission data.

[Example] Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment according to the present invention. In FIG. 1, as in FIG. 3, the left side of the broken line P is the data transmitting side T, and the right side is the data receiving side R.

In the figure, 1 is the same data supply unit as in FIG.
3 is an oscillation circuit that outputs a clock whose transmission time per data bit is a half cycle; 3 is a data string Di, D2, D3, . D4. D5. ...of...
Di, D3°D5. . . , at the rising edge of the transmission clock 12, the transmission latch circuit A,4 latches D2. D4. This is a transmission latch circuit B that latches . . . at the falling edge of the transmission clock 12. The latch circuits A and B (3, 4) for transmission have output permission input terminals E1. :
When “Low” level is input, the output is in a high impedance state and “High” is applied to the Eef4 child input.
If the level is set manually, follow the latch data and “
It is composed of a known tri-state output latch circuit that outputs a "Low" level or a "High" level. 5 and 9 are inverter circuits, 6 is a delay circuit, and the delay circuit 6 applies a predetermined amount to the transmission clock 12. In this embodiment, delay processing is performed at 1/4 of the transmission clock.
A delay equal to the period is applied. 7 is the reception clock 16
Receiving latch circuits A and 8, which latch the received data string 15 on the transmission line 13 at the rising edge of the reception clock, are receiving latch circuits B which latch the received data string 15 at the falling edge of the receiving clock, and these latch circuits also latch the received data string 15 on the transmission path 13. Like the reliable latch circuit, it is a tri-state output. Further, 10 is a data processing section similar to that shown in FIG. 35. Note that the latch circuit and transmission line of this embodiment may be of a type that transmits each bit in series, or of a type that transmits a plurality of bits in parallel. When transmitting in parallel, the number of transmission lines and each latch circuit may be equal to the number of parallel bits.

FIG. 2 shows the data transmission timing of this embodiment having the above configuration.

Data strings DI, D2 . D3゜D4. D5.・
... are sequentially output and input to the transmitting latch circuits A3 and B4. The respective latch circuits A3 and B4 alternately latch this data string at the rising and falling edges of the transmission clock 12, as described above. For example, Di, D3.
D5. ... is connected to the transmitting latch circuit A3, D2. D4.
D6. ... are respectively latched by the transmission latch circuit B4. On the other hand, each latch circuit has an input E terminal “
The output is energized only in the "High" section, and the high impedance state is maintained in the "Low" section. Therefore, as shown in the figure, the transmitting latch circuit A3 is activated in the sections TI, T3.T5.
．． . . ., the transmitting latch circuit B4 operates only during the interval T2.
T4. The output of each latch data is valid only in the section of ....

Therefore, the transmission data on the transmission line 13 is the data string DI,
D2. D3. D4. D5. ... are sequentially output as shown in the timing chart. Also, the reception clock 16 at this time is delayed by 1/4 cycle due to the action of the delay circuit 6, and the reception latch circuit A7 and the reception latch circuit B8 detect the rising edge of the reception clock 16 and the reception latch circuit B8.
The transmission data is latched at the falling edge of the signal. Therefore, even if the latch timing is slightly off, data can be reliably captured when the data is in a stable state.

The reception latch circuit A7 has Di, D3. D5. ···of,
The reception latch circuit B8 is D2. D4. ... are each latched. Then, the data processing unit 10 stores continuous data strings Di, D2 . D3. D4. ...is received data 17
is entered as .

As explained above, according to this embodiment, data transmission is performed in synchronization with a clock having the same frequency as the maximum frequency of the carrier frequency of transmitted data, and furthermore, the receiving clock is compared with the transmitting clock, and the necessary amount is By transmitting the digital data with a delay of 100 seconds, it is possible to reliably transmit the digital data to be transmitted while synchronizing it with this receiving clock without being affected by waveform distortion during transmission.

Furthermore, since the frequency of the synchronization clock used for transmission is set to be the same as the maximum frequency of the carrier frequency of the transmission data, the frequency of this synchronization clock can be reduced to 1/2 of the conventional frequency. This improves the reliability of data transmission and allows the speed of peripheral ICs to be reduced.

It also has a great effect on suppressing unnecessary radiation from the transmission path.

[Effects of the Invention] As explained above, according to the present invention, reliability in digital data transmission can be greatly improved, and the device does not require a high-speed device, is inexpensive, and has high reliability. can be taken as a thing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment according to the present invention, Fig. 2 is a transmission control timing chart of this embodiment, Fig. 3 is a block diagram of a conventional data transmission circuit, and Fig. 4 is a conventional transmission control timing chart. It is a chart. In the figure, 1 and 31 are data supply units, and 2 and 32 are oscillation circuits 3.
, 4, 7, 8, 33.34 are latch circuits, 6 is a delay circuit, and 10.35 is a data processing section.

Claims (3)

[Claims] (1) A data transmission method for transmitting digital data via a communication medium, characterized in that data transmission is performed in synchronization with a clock having the same frequency as the maximum transmission frequency of transmitted data on the communication medium. Data transmission method. (2) A data transmission circuit that performs digital data transmission via a communication medium, which includes a first latch means that latches the digital data to be transmitted at the rising edge of a synchronous timing signal, and a first latch means that latches the digital data to be transmitted at the rising edge of a synchronous timing signal. a second latch means that latches at the falling edge of the synchronous timing signal; and a selection means that alternately selects and outputs the output from the second latch means and the output from the first latch means, A data transmission circuit characterized by outputting digital data in synchronization with rising and falling edges. (3) The data transmission circuit according to claim 2, wherein the first latch means and the second latch means output high impedance when the output is not selected by the selection means.