JPH01186032A - Data output device - Google Patents

Abstract

PURPOSE:To ensure the set and hold time and to surely transmit a data even if the edge operation at the input and output side is opposite to each other by latching a data with a latch clock of a system transmitting the data from an output device to an input device and generating a phase difference with the clock sent to the input side. CONSTITUTION:The 1st clock is outputted from a clock output circuit 1 of a data output circuit, and a data is generated from a data generating circuit 2 synchronously with the clock. the data is latched in a data latch circuit 3 by using a 1st clock as the latch clock. The phase of the 1st clock is shifted by a phase shift circuit 4, a 2nd clock from the circuit 4 is used as the clock output and sent to the input device and the latch data is outputted from the latch circuit 3. A 3rd clock is generated by a clock generating circuit 5 of the clock output circuit 1, the 3rd clock is frequency-divided by an FF 6, an inverter 7 inverts the 3rd clock to output the 1st clock.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a data output device in a data transmission system in which data is transmitted from an output device to an input device according to the edge of a clock, and relates to a device that outputs digital data, a tC, etc. This applies to

<Prior art> Generally, when transmitting digital data from an output device to an input device in synchronization with a clock, digital data is transmitted according to either the rising or falling edge of the clock determined by the output device. Data is transmitted.

For example, as shown in FIG. 4, data is transmitted at a timing such that data is output at the rising edge of the clock and read into the input device at the falling edge. In this case, if the device on the input side operates at the opposite edge to the device on the output side, that is, if data is read on the rising edge, the clock must be inverted by adding an inverter, etc. For example, since there is no hold time at all at the rising edge of the clock, data input may not be guaranteed depending on the characteristics of the transmission path.

<Object of the Invention> The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to ensure that data is reliably captured on the input side regardless of the difference in edge operation between the output side and the input side. The purpose is to provide a data output device.

<Configuration of the Invention> In order to achieve the above object, the present invention includes a clock output circuit, a data generation circuit that generates data in synchronization with the clock of the clock output circuit, and a clock of the clock output circuit that latches the clock of the clock output circuit. A data output device comprising a data latch circuit that latches data from the data generation circuit as a clock and timing data transmission according to an edge of the clock, wherein a phase shift circuit shifts the phase of the clock of the clock output circuit. Alternatively, a delay circuit is provided so that the phase-shifted clock and the output of the data latch circuit are transmitted.

According to the above configuration, by creating a phase difference between the latch clock for latching data and the clock output to the input side, the timing of the clock and the output data is shifted. Setup time and hold time can be secured, and even if the edge operations on the output side and the input side are reversed, data can be reliably captured on the input side without providing an inverter or the like.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which data and clocks are transmitted to input devices (not shown).

The data output device of this embodiment includes a clock output circuit 1 that outputs a first clock, a data generation circuit 2 that generates data in synchronization with the first clock, and a clock that generates the data using the first clock as a synchronized clock. It is provided with a data latch circuit 3 that latches data from the circuit 2, and the above configuration is basically the same as that of the conventional example.

Furthermore, this embodiment is provided with a phase shift circuit 4 for shifting the phase of the first clock, and the second clock from this phase shift circuit 4 is transmitted as a clock output to an input device (not shown). The output of the data lab circuit 3 is transmitted.

FIG. 2 is a configuration diagram showing details of the main parts of FIG. 1, and FIG. 3 is a timing chart for explaining the operation.

The clock output circuit 1 that outputs the first clock shown in FIG. , a D flip-flop 6 that divides the frequency of this third clock by two, and an inverter 7 that inverts the third clock.

This clock output circuit 1 outputs the first clock shown in FIG. 3(C) to the data generation circuit 2, data latch circuit 3, and phase shift circuit 4.

The data latch circuit 3 is composed of a D flip-flop, receives the first clock from the clock output circuit 1 as a latch clock, and outputs the data shown in FIG. 3(A). That is, the data transmission timing is determined by the first clock.

A phase shift circuit 4 for shifting the phase of the first clock from the clock output circuit 1 is composed of a D flip-flop,
Based on the clock from the inverter 7 of the clock output circuit 1, the phase of the first clock is shifted by 90 degrees as shown in FIG.
B) outputs the second clock shown in FIG.

As shown in the data output and clock output of FIGS. 3(A) and 3(B), the second clock is shifted in phase from the first clock.
By using the clock as a clock output, the timing between the clock output and the data determination period T can be shifted compared to the conventional example shown in FIG. Time A1. B1. and hold time A 2.8
2 is ensured, and the same data can be obtained at either the rising or falling edge of the clock output.

Therefore, even if the edge operations on the output side and the input side are reversed, data can be reliably captured on the input side without the need for an inverter, making it possible to modify a large number of input devices with different edge operations. This means that it can be connected to the output device of the present invention.

In the above embodiment, the phase shift circuit 4 is provided, but in other embodiments of the present invention, a delay circuit may be provided in place of the phase shift circuit 4.

Further, in the above-described embodiment, an example in which 1-bit data is transmitted has been described, but it goes without saying that the present invention can be similarly applied to data of multiple bits.

<Effects of the Invention> As described above, according to the present invention, a phase difference is created between the latch clock for latching data and the clock transmitted to the input side, thereby reducing the setup time and hold. Even if the edge operations on the output side and the input side are reversed, data can be reliably captured on the input side without the need for an inverter or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing chart for explaining the operation, and FIG. 4 is a timing chart of a conventional example. l...clock output circuit, 2... data generation circuit,
3...Data latch circuit, 4...Phase shift circuit.

Claims (1)

[Claims] (1) A clock output circuit, a data generation circuit that generates data in synchronization with the clock of this clock output circuit,
A data output device comprising a data latch circuit that latches data from the data generation circuit using the clock of the clock output circuit as a latch clock, the data output device timing data transmission according to the edge of the clock; A data output device characterized in that a phase shift circuit or a delay circuit is provided for shifting the phase, and the phase-shifted clock and the output of the data latch circuit are transmitted.