JPS62281632A - Timing control circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit which controls the timing between devices by providing a latch circuit which latches the data to be transferred between devices and a delay circuit which delays the control signal received from the transmission side and controls the data transfer timing to the reception side from the latch circuit. CONSTITUTION:The data D outputted from the 1st device 1 with the fixed relation with a clock signal CL0 is set to a latch circuit 3 according to the state of the 1st control signal CL1. While the 2nd control signal CL2 is delayed by a delay circuit 4 in relation to the signal CL0. Then the data D set to the circuit 3 is supplied to the 2nd device 2 while the signal CL2 is supplied. The data D received by the device 2 is delayed by the time set based on the delay time of the signal CL2 and in relation to the clock signal.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In data transmission between devices, there is a latch circuit that latches data for transfer between the devices, and a control signal from the transmitting side that is delayed and transmitted from the latch circuit. By providing a delay circuit that adjusts the timing of transfer to the receiving side, the timing adjustment circuit between devices is simplified.

[Industrial application field]

The present invention relates to a timing adjustment circuit for inputting data from a first device to a second device at regular timing.

[Conventional technology]

In some types of control systems, for example, as shown in FIG. 4, a central processing unit (hereinafter referred to as CPU) 10
l10LSI30 interfaces with the outside from
When transferring data to the
) and outputs data (Da t0) in a certain relationship with this E-C1ock.
As shown in figure (0), data is started Δto1 after starting E-C:Iock, while E-Clo
The data falls after Δto2 from immediately before the fall of ck.

Also, at this time, l10LSI30 is the above E-C1oc
k is input, and data input at a certain timing is recognized based on this E-C1ock.

Therefore, for example, if the timing of data output from CPU10 is as shown in FIG. 5 (0), l10LSI3
0 must be capable of recognizing input data from the time Δto1 has elapsed since the rise of E-C1ock (time 1+) to the time Δ702 has elapsed from just before the fall of E-C1ock (time tz). .

By the way, when determining circuit elements during circuit design,
Factors such as cost, mounting area, and performance must be considered, but due to cost, power consumption, etc., the fifth
C that outputs data at the timing shown in the figure (&)
l10LS that satisfies the above requirements (data recognition between time t1 and t2 in Fig. 5 (0)) for PUl0
It may be advantageous to connect l10LSIs other than I. In this case, if you try to use the l10LSI, C
Data from PU10 is sent to l10L at regular timing.
A timing adjustment circuit is required to input the signal to the SI.

Specifically, for example, as shown in FIG. 5(b), E-Cl
Data recognition is not guaranteed unless the input data is held for ΔtL from the falling edge of IE-Cock./In the case of LSI, the data from CPU10 has already fallen at the falling edge of IE-C1ock (see Figure 5). 0)) Therefore, the data from CPUl0 is E-C1oc.
A delay circuit is required in relation to k.

Here, in a circuit as shown in FIG.
l10LSI3 by delaying the data from by a predetermined time.
0, generally CPUl0 and l10LSI3
It is conceivable to provide a delay circuit in the data line provided between 0 and 0.

[Problem that the invention seeks to solve]

A first device such as the above CPU10 and l10LSI30
If the timing adjustment circuit to be constructed between the second device and the like is a delay circuit provided on the data line between each device, the circuit scale of the timing adjustment circuit will be relatively large.

This is because data transmitted between devices is generally composed of multiple bits, so there are multiple data lines, and accordingly, a delay circuit is provided for each of the multiple data lines.

For example, when a delay circuit is constructed of ordinary gates, 24 gates are required considering the delay caused by three stages of gates for 8-bit data. Furthermore, the fact that the number of gates must be simply increased in accordance with the number of data bits poses a problem, for example, in terms of power consumption for driving the gates.

Therefore, it is an object of the present invention to avoid the need to provide a delay circuit for each data line between the first device and the second device.
data from one device is delayed and provided to a second device.

[Means for solving problems]

In the present invention, as shown in FIG.
A first device 1 that outputs data D along with the clock signal CLo in a certain relationship with the clock signal CLo, and the clock signal CL for properly recognizing the data D from the first device 1.

It is assumed that a timing adjustment circuit is configured between the second device 2 and the second device 2 which requires a delay of the data D in relation to the above, and the technical means for solving the above problem in the timing adjustment circuit are as follows. The above clock signal CLo
The data D from the first device 1 is set according to the state of the first control signal CL based on the clock C.
A latch circuit 3 that provides the set data D to the second device 2 while the second control signal CL2 based on LO is input.
and a delay circuit 4 that delays the second control signal CL2 with respect to the latch circuit 3 by a predetermined time.

[Effect]

Data output from the first device 1 in a certain relationship with the clock signal CL is stored in the latch circuit 3 according to the state of the first control signal CL. And the second
The control signal CL2 is converted into the clock signal C by the delay circuit 4.
The data D, which is delayed in relation to LO and is set in the latch circuit 3 while the second control signal CL2 is input, is provided to the second device 2. Here, the second
The data D provided to the device 2 is delayed in relation to the clock signal by a time based on the delay time of the second control signal.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit diagram showing an example of a timing adjustment circuit according to the present invention, and portions surrounded by broken lines indicate correspondence with FIG. 1 and are assigned the same numbers.

In the figure, 10 is a CPU, and this CPU10 receives various control signals, such as read (H level) φ write (L
level) signal (hereinafter referred to as R/W signal), E-Clock as described above, and VM, A signal (H level indicates data output state), and this R/W signal.
When the W signal is at the L level and the VMA control signal level, data D is input in a predetermined relationship with E-C:1ock.
Further, each address A is output at a predetermined timing. 11 is a bidirectional transceiver whose directionality is determined by the state of the R/W signal.N12 is a transparent latch (hereinafter referred to as TP) that performs a predetermined latch operation based on control signals input to LE and OE, which will be described later.
CPUI via transceiver 11
Data from o is set in TPL12. Here, the specific functions of TPL 12 are as follows:
Input data (I
N), while the set data is output (OlJT) while the signal input to OE is at L level.

Looking at the various control signals output from CPUl0, the R/W signal is sent via the VMA control signal driver 21, the R/W signal is sent via the driver 22, and the E-Clock is sent to the driver 23.
The signals are respectively input to the Nant gate 25 via the Nant gate 25, and the output of the Nant gate 25 serves as the read enable signal RE. Further, the VMA control signal is sent via the driver 21, and the R/
The W signal and E-C1ock are input to the Nantes gate 26, and the output of this Nantes gate 26 is the write enable signal WE. And CPU10-1, Ln
-Efu l''!In-re, ^<71'TI'l> (1)
■WVU128 output @> is input, while the above write enable signal WE is the gate 1 of the three stages as a delay circuit.
It is input as another control signal to the oE of TPL12 via 5.16.17.

Note that the E-C1ock, write enable signal WE, and read enable signal RE from the CPU 10, which is the first device, are directly input to the second device (not shown) such as the 110LSI, and the data D from the CPU 10 is also directly input. is input via a transceiver 11 and TPL 12.

In addition, the address A from CPU10 is the TPL12 mentioned above.
The configuration is similar to that of , and data is supplied to the second device via another TPL 14 in which LE is always fixed at H level and OE is fixed at L level, while data from the device in the section 2 is supplied to the read enable signal. The signal is input to the CPU10 via the unidirectional transceiver 13 enabled by the RE and the bidirectional transceiver 11.

Next, the operation of the timing adjustment circuit will be explained according to the timing chart shown in FIG.

CPtJIO together with E-C1ock, this E-C1
ock, data is output in a relationship substantially similar to that shown in FIG. 5 (0), and specifically, the data is
Assume that the second device is guaranteed to recognize the data held until Δ1 (from the falling edge of E-C1ock) while the second device falls after tpd2 has elapsed from just before the falling edge of E-C1ock.

The data output from CPUl0 is transceiver/<11
This input data is input to the TPL 12 via the transceiver 11, but due to the delay in the transceiver 11, its rising edge is
d+, the same falling edge is tpc13 (the above CPUl
It is delayed from the output timing from 0. At this time, T
Since E-C1ock input to I and E of PL12 is in the H level state, the input data is set in TPL12.

On the other hand, the write enable signal WE is basically E-C1o.
This is an inverted signal of ck, but due to the delay in the Nandt gate 26 etc., it is output from the Nandgate 26 with a delay of tpd4 with respect to the E-C1ock, and is further outputted from the Nandgate 26 with a delay of tpd4 from the E-C1ock.
．． 16. Due to the delay in 17, EPds is delayed by T.
PL12 (7) OEi: Input.

Therefore, the write enable signal WE is E-C1oc.
The relationship is delayed by tpda + tPds with respect to k (actually, with respect to the inverted signal of E-C1ock), and the TPL 12 outputs the set data while the write enable signal WE is falling. Regarding the specific timing, due to the delay in the TPL 12, the write enable signal W
With E falling, tl)d from the relevant data input
When 8 elapses, the data output is raised and this state is maintained, while after the write enable signal WE rises to H level, the tidy elapsed time output is lowered.

As a result, the data output from TPL12 is
Using ck as a reference, tpd4 + tpds + tpd7 = Δt... from just before the falling edge of E-C1ock.
(1) will be delayed. And this Δ is Δ shi > tpdo + Δt... (2) t
Pda: If the fall time condition of E-C1ock is satisfied, when the second device inputs data via the TPL 12, the data is reliably recognized.

As described above, according to this embodiment, if the control signal (WE) input to the OE of TPL l 2 is delayed with respect to the E-Clock so as to satisfy the above equation (2), the second It is possible to guarantee reliable data recognition in the device.

〔Effect of the invention〕

As described above, according to the present invention, data from the first device can be delayed without providing a delay circuit for each data line between the first device and the second device. Second
Therefore, the circuit scale of the timing adjustment circuit can be made relatively small.

LM surface/section 7-1 single-stop hit FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a circuit diagram showing an example of the timing adjustment circuit according to the present invention, and FIG. 3 is the timing adjustment shown in FIG. 2. FIG. 4 is a timing chart showing the operation of the circuit, FIG. 4 is a block diagram showing the connection state between the CPU and 110LSI, and FIG. 5 is a timing chart showing the relationship between E-C1ock and data.

1... First device 2... Second device 3...
Latch circuit 4...Delay circuit 10...CPU 12...Transparent latch (TPL) 1
5.116.17...Gate 10 3゜Figure 4 (b) E-C1ock't data relationship 1 minus timing °nate 5th Wi

Claims (1)

[Claims] A first device (1) that outputs data (D) together with a predetermined clock signal (CL_0) in a certain relationship with the clock signal (CL_0); and from the first device (1). In order to properly recognize the data (D), the second data (D) must be delayed based on the timing relationship with the clock signal (CL_0).
A timing adjustment circuit configured between the device (2) and the device (2), the timing adjusting circuit configured to control the data (D) from the first device (1) according to the state of the first control signal (CL_1) based on the clock signal (CL_0). ) and also set the same clock signal (CL
a latch circuit (3) that provides the set data (D) to the second device (2) while a second control signal (CL_2) based on the second control signal (CL_2) based on the second control signal (CL_2) is input; A timing adjustment circuit comprising: a delay circuit (4) that delays the latch circuit (3) by a predetermined time.