JPH11331281A - Data retiming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a data retiming circuit not affected by delay in input data. SOLUTION: Clocks CLKa-CLKn generated by an ST clock generating circuit 2 have the same frequency as that of a clock timing ST but phases different from that of the timing ST. Window pulses PWa-PWn are respectively given to AND circuits 5a-5n and ANDed with a differentiation pulse DP generated by a differentiation circuit 3. A control circuit 7 discriminates a clock whose phase is closest to the phase of data SD based on the pulse signal detected by pulse detection circuits 6a-6n and selects an optimum clock by controlling a selector 8. A flip-flop 1 applies re-timing to the data SD by receiving a clock with an optimum phase selected by the selector 8 and inverted by an inverter 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data retiming circuit, and more particularly to a data retiming circuit of a communication modem.

[0002]

2. Description of the Related Art When data is transmitted from a terminal device to a modulation / demodulation device, as shown in FIG. 6, the data is synchronized at the clock timing of the terminal device 30 (FIG. 6).
(see FIG. 6A) and a method of transmitting at the clock timing on the modem 20 side (see FIG. 6B). The present invention relates to a case where data is transmitted at the clock timing of the modem 20 side.

When data is transmitted using the clock timing of the terminal device 30, the delay of the data SD (send data; transmission data) is ignored with respect to the clock TT (terminal timing; clock timing of the terminal device 30). As little as possible.

On the other hand, when data is transmitted using the clock timing on the modem 20 side, a clock ST (send timing; transmission timing) is transmitted from the modem 20 to the terminal device 30, and the terminal device 30 transmits the clock ST at the timing of the received clock ST. In the data SD, the modem 20
And the data SD is received by the modem 20.

[0005]

As shown in FIG. 6B, when data is sent from the terminal device 30 to the modem 20 at the clock timing on the modem 20 side, the clock timing ST output from the modem 20 is changed to the clock timing ST output from the modem 20. On the other hand, since the data SD input to the modulation / demodulation device 20 is delayed, there is a problem that data retiming may be inconvenient in the modulation / demodulation device 20 depending on the delay amount.

That is, when data retiming (synchronizing the timing of data and clock) is performed in the modem 20, the input data (data SD) from the terminal device 30 is converted to the data as shown in FIG. The clock ST of the modem 20 is inverted in phase by the inverter 10 and latched (reread) by the flip-flop (for example, data type flip-flop) 1 to perform retiming.

The clock ST is generated by the ST clock generation circuit 2, and the clock ST whose phase has been inverted by the inverter 10 is supplied to the data processing circuit (see FIG. (Not shown). However, if the phase delay of the data SD with respect to the clock ST (in the modem 20) is large, the latch time in the flip-flop 1 becomes insufficient and the latch operation becomes impossible.

The reason why the data SD is delayed with respect to the clock ST (in the modem 20) is that the following total delay occurs in the data SD. That is, the total delay amount is: total delay amount = (clock transmission delay in modem 20) + (clock propagation delay from modem 20 to terminal device 30) + (delay in terminal device 30 + terminal device 30 It is represented by (data propagation delay to the modem 20) + (data delay in the modem 20).

Of these delays, the clock propagation delay from the modem 20 to the terminal 30 and the delay of the terminal 30
The data propagation delay from to the modem 20 varies with the cable length between the terminal device 30 and the modem 20;
Delay for several ns per meter of cable. Therefore, the influence is great when the cable length is long or when the transmission speed is high.

An object of the present invention is to provide a data retiming circuit which is not affected by the delay amount of data SD.

[0011]

A data retiming circuit according to the present invention sends back a first clock from a modem to a terminal, and the terminal transmits data synchronized with the first clock to the modem. A data retiming circuit of the modulation / demodulation device in the system, wherein the second clock generation means for generating a plurality of second clocks having different phases sequentially in synchronization with the first clock; and A window pulse generating means for generating a plurality of window pulses sequentially formed adjacent to a base, a data phase detecting means for comparing a phase between the window pulse and an end of the data, and a data phase detecting means. Retiming clock generating means for selectively generating a retiming clock from the second clock based on an output; Characterized in that it comprises a data retiming means for retiming the lock.

Further, the second clock is constituted by n clocks shifted by 2π / n times the phase of the first clock with respect to the first clock. The window pulse is constituted by n pulse trains having a window having a width of 2π / n times the first clock cycle and shifted by 2π / n times the first clock cycle. I do.

Further, the data phase detecting means includes:
By selectively detecting the window pulse corresponding to the phase of the data by taking the logical product of the differential pulse corresponding to the rising portion and the falling portion of the data and each of the n window pulses, Further, the retiming clock generating means selects the second clock corresponding to the window pulse detected by the data phase detecting means as a retiming clock.

The operation of the present invention is as follows. When the data SD sent from the terminal device is delayed with respect to the clock timing ST of the modem, a clock having an optimal phase for retiming the data SD is generated in the modem. That is, n (book) clocks having different clock timings ST and phases are generated,
Among these n (book) clocks, the clock closest to the phase of the data SD is determined. As a result, a clock having the optimum phase is selected, and the data S
D can be retimed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a data retiming circuit of a modem according to the present invention. In FIG. 1, a data retiming circuit according to the present invention includes a flip-flop circuit 1 for retiming (latching) input data SD, clock timings ST and n having the same frequency as ST and different phases from each other.
ST for generating clocks CLKa to CLKn
A clock generation circuit 2 includes a differentiating circuit 3 that generates a differential pulse DP at a change point of the input data SD.

The data retiming circuit according to the present invention uses n (number) clocks CLK1 to CLKn.
A window pulse generating circuit 4 for generating window pulses PWa to PWn; AND circuits 5a to 5n for obtaining a logical product of the differential pulse DP and the window pulses PW1 to PWn; and AND circuits 5a to 5n
Pulse detection circuits 6a to 6 for detecting the pulses of the output signal of
n, a control circuit 7 for determining (selecting) a clock having an optimal phase based on the detection results of the pulse detection circuits 6a to 6n.

Further, the data retiming circuit according to the present invention uses the optimum clock C determined by the control circuit 7.
The selector 8 includes a selector 8 for selecting LKa to CLKn, a reference clock source 9 for driving the ST clock generation circuit 2, and an inverter 10 for inverting the phase of the output of the selector 8.

The operation of the embodiment of the present invention will be described. In FIG. 1, an ST clock generation circuit 2 generates a clock timing ST based on a reference clock generated by a reference clock source 9.
And the clocks CLKa to CLKn. Each of the clocks CLKa to CLKn is a clock train having the same frequency as the clock timing ST and a different phase only, and is a clock train in which the phases are sequentially shifted at an interval of 2π / n radians. That is, assuming that the phase of CLKa is φ, the phase of CLKb is (φ + 1 × 2π /
n), the phase of CLKc is (φ + 2 × 2π / n),.
The phase of LKn is (φ + (n−1) × 2π / n).

The clock timing ST is sent to the terminal device 30, and the terminal device 30 receives the clock timing ST.
Is output to the modem 20. The data SD sent from the terminal device 30 is retimed by the flip-flop 1 and input to the differentiating circuit 3 to generate a differential pulse DP corresponding to the end (rising and falling) of the data SD.

C generated by the ST clock generation circuit 2
LKa to CLKn are input to the selector 8 and converted into window pulses PWa to PWn by the window pulse generation circuit 4. The window pulses PWa to PWn are AND circuits 5a to 5n
To the differential pulse DP generated by the differentiating circuit 3 and the logical product is obtained.

The timing relationship at this time is as shown in FIG. 2 when the input data SD is delayed from the clock (timing) ST by the delay amount τ, and the window pulse PW
Only the AND circuit (AND5c in the example shown in FIG. 2) outputs a pulse at a timing when a to PWn coincide with the differential pulse DP. The pulse detection circuits 6a to 6n monitor the outputs of the AND circuits 5a to 5n and detect output pulse signals.

The control circuit 7 determines the clock having the phase closest to the phase of the data SD based on the pulse signals detected by the pulse detection circuits 6a to 6n, and selects the optimum clock by controlling the selector 8.

That is, from the window pulse (for example, PWc) corresponding to the AND circuit at the timing when the window pulses PWa to PWn coincide with the differential pulse DP, the clock (for example, CLK) corresponding to this window pulse (for example, PWc)
Select c) as the optimal clock. The flip-flop 1 inverts the phase of the clock of the optimum phase selected by the selector 8 by the inverter 10 to re-time the data SD. The clock of the optimum phase is supplied to the inverter 10
The reason for retiming the data SD after phase inversion is that accurate data latching is difficult if retiming (latch) is performed near the level transition of the data SD. Therefore, the data is latched at an intermediate point of the stable level transition. Therefore, the inverter 10 inverts the phase of the latch clock to shift the latch timing by 90 degrees.

FIGS. 3 and 4 show examples of the configuration of the ST clock generation circuit 2. FIG. FIG. 3 is a configuration example using a delay circuit.
The clock from the reference clock source 9 having the same frequency as the clock (timing) ST is converted into delay circuits DLYa to DLY (n-1) each having a delay of 2π / n radians.
Clocks CLKa to CLKn
Generate

FIG. 6 shows a configuration example using a frequency dividing circuit and a shift register. It has a reference clock source 9 of n times the frequency of the clock (timing) ST, divides the reference clock by n by the frequency dividing circuit CTR,
T and CLKa are generated. Shift registers SRa-S further operating on the generated CLKa with a reference clock
By delaying by R (n-1), CLKb
To CLKn.

FIG. 5 shows a configuration example of the window pulse generation circuit 4. In FIG. 5, for example, using the clocks CLKa to CLKn generated by the ST clock generation circuit 2,
The window pulse PWa is changed to CLKn by the D circuits 12a to 12n.
And CLKa. Similarly, PWb is generated by CLKa and CLKb, PWc is generated by CLKb and CLKc,..., PWn is generated by CLKn-1 and CLKn, respectively.

[0027]

As described above, the present invention always optimizes the data SD in the modem even if the data SD sent from the terminal device is delayed with respect to the clock timing ST of the modem. The retiming can be performed at an appropriate timing, and there is an effect that stable synchronous data transmission can be performed.

That is, an optimal retiming clock is generated in accordance with the delay of the data SD.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of an ST clock generation circuit.

FIG. 4 is a block diagram of another example of the ST clock generation circuit.

FIG. 5 is a block diagram illustrating an example of a window pulse generation circuit.

FIG. 6 is an explanatory diagram of data transfer between a terminal device and a modem.

FIG. 7 is a block diagram of a conventional data retiming circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 flip-flop 2 ST clock generating circuit 3 differentiating circuit 4 window pulse generating circuit 5 a to 5 n AND circuit 6 a to 6 n pulse detecting circuit 7 control circuit 8 selector 9 reference clock diagram 10 inverter

Claims (6)

[Claims] 1. A data retiming circuit of a modem in a system in which a first clock is sent back from a modem to a terminal, and the terminal transmits data synchronized with the first clock to the modem. A second clock generation means for generating a plurality of second clocks having different phases sequentially in synchronization with the first clock; and a plurality of windows formed in a form adjacent to each other based on the second clock. Window pulse generating means for generating a pulse; data phase detecting means for comparing the phase of the window pulse with the end of the data; and a retiming clock from the second clock based on the output of the data phase detecting means. Clock generating means for selecting and generating, and data retiming means for retiming the data by the retiming clock And a data retiming circuit. 2. The method according to claim 1, wherein the second clock is composed of n clocks that are shifted from the first clock by 2π / n times the first clock cycle. Item 2. A data retiming circuit according to Item 1. 3. The window pulse comprises n pulse trains having a window having a width of 2π / n times the first clock period and shifted by 2π / n times the first clock period. 3. The data retiming circuit according to claim 1, wherein the data retiming is performed. 4. The data phase detecting means calculates a logical product of a differential pulse corresponding to a rising part and a falling part of the data and each of the n window pulses to correspond to a phase of the data. 4. The data retiming circuit according to claim 1, wherein said window pulse is selectively detected. 5. The retiming clock generating means,
5. The data retiming circuit according to claim 1, wherein said second clock corresponding to said window pulse detected by said data phase detecting means is selected as a retiming clock. 6. The data retiming circuit according to claim 1, wherein said data retiming means latches said data by said data retiming clock.