KR100210901B1 - Correcting circuit of data transmission system - Google Patents

Abstract

The present invention relates to a data transmission / reception system for transmitting and receiving data, and more particularly, to a data correction circuit of a data transmission / reception system that allows a receiving side to receive corresponding data without loss when transmitting data.

In the conventional data transmission / reception system, when the transmitting side transmits data at the rising edge of the clock and the receiving side receives the data applied from the transmitting side at the rising edge of the clock, the minimum data hold time at the transmission path is not maintained. Due to this, there was a problem that the receiving side could not read the data correctly and lost.

According to the present invention, when the transmitting side transmits data at the rising edge of the clock and the receiving side receives the corresponding data at the rising edge of the clock, the receiving side corrects the data so that sufficient data hold time is maintained and applied to the receiving side. The data will be received without loss.

Description

Data correction circuit of data transmission / reception system

The present invention relates to a data transmission / reception system for transmitting and receiving data, and more particularly, to a data correction circuit of a data transmission / reception system for allowing a receiving side to receive corresponding data without loss when data is transmitted from a transmitting side.

In general, in the case of transmitting and receiving data, data can be successfully transmitted and received only if the receiving side can receive the data transmitted without any loss.

In the related art, data is transmitted and received in the manner shown in FIG. 1. That is, the transmission module 10 transmits data to the receiving module 20 side, and transmits data according to the frame synchronization signal FS and the clock applied from the receiving module 20. When the transmitting module 10 transmits data to the receiving module 20 side, as shown in FIG. 2, the transmitting module 10 transmits the data according to the frame synchronizing signal FS and the clock. Data is transmitted at the rising edge, and the receiving module 20 receives data at the rising edge of the corresponding clock. On the other hand, when the transmitting module 10 transmits data at the rising edge of the clock, the data reaches the receiving module 20 after the clock slightly rises as shown in FIG. Because the data hold time (about 20 ns) is not maintained, the reception module 20 cannot read valid data at the rising edge of the clock. In more detail, as shown in FIG. 3, when the transmitting module 10 transmits data at the rising edge 31 of the clock, the receiving module 20 does not read data at the rising edge 31 of the clock, but at the rising edge 1. Will be read. At this time, in order for the receiving module 20 to read data at the rising edge 1 of the clock, the minimum data hold time must be maintained on the transmission path. However, since the corresponding data hold time cannot be maintained, the corresponding data is lost and read valid data. There is a problem that can not be entered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a data correction circuit of a data transmission / reception system that allows a receiving side to receive corresponding data without loss when the transmitting side transmits data.

The present invention for achieving the above object comprises: a receiving module for outputting a frame synchronization signal and a clock through a transmission path, and receiving data applied through the transmission path according to the clock; A data transmission / reception system including a transmission module for receiving a frame synchronizing signal and a clock applied from a receiving module through a transmission path and transmitting data to the receiving module according to the clock, wherein the data is transmitted from the transmitting module. A first delay circuit configured to delay and output a first predetermined period of the clock according to the frame synchronization signal and a clock; And a second delay circuit for delaying data applied from the first delay circuit by a second predetermined period of the clock and outputting the data to the receiving module side in accordance with the frame synchronizing signal and a clock. The data hold time is maintained at the time of reception.

As described above, the present invention transmits data at the rising edge of the clock, and when the receiving side receives the data at the rising edge of the clock, the receiving side corrects the data so that sufficient data hold time is maintained and applied to the receiving side. The side will receive the data without loss.

1 is a block diagram showing a conventional data transmission and reception system.

2 and 3 are waveform diagrams for explaining the operation of the data transmission and reception system shown in FIG.

4 is a block diagram showing a data transmission and reception system according to the present invention.

5 is a configuration diagram of a data correction circuit shown in FIG.

6 and 7 are waveform diagrams for explaining the operation of the data correction circuit.

* Explanation of symbols for main parts of the drawings

10: transmitting module 20: receiving module

30: data correction circuit 31: first delay circuit

32: second delay circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 4, the data transmission / reception system according to the present invention includes a transmission module 10, a reception module 20, and a data correction circuit 30. The transmission module 10 transmits data from the reception module 20 to the reception module 20 in accordance with the frame synchronization signal FS and a clock applied through the data correction circuit 30. The data correction circuit 30 transmits the frame synchronizing signal FS and the clock applied from the receiving module 20 to the transmitting module 10 and simultaneously transmits the data applied from the transmitting module 10 to the corresponding frame synchronizing signal ( FS) and delay correction according to the clock so that the minimum data hold time is maintained and outputted to the receiving module 20 side. The receiving module 20 receives data according to a frame synchronization signal FS and a clock which are transmitted to the transmitting module 10 side.

Meanwhile, as illustrated in FIG. 5, the data correction circuit 30 includes a first delay circuit 31 and a second delay circuit 32. The first delay circuit 31 delays and outputs the data applied from the transmission module 10 according to the frame synchronizing signal FS and a clock. The second delay circuit 32 delays the applied data by a half cycle of a clock. Output to the side. The second delay circuit 32 delays and outputs the data applied from the first delay circuit 31 according to the frame synchronizing signal FS and a clock. The second delay circuit 32 outputs data applied from the first delay circuit 31 to the clock 15. Delayed by a cycle and outputs to the receiving module 20 side. As such, since the data correction circuit 30 delay-corrects the data applied from the transmission module 10 to maintain the minimum data hold time, the data correction circuit 30 outputs the data to the reception module 20. Receive correctly.

The data correction circuit 30 configured as described above operates as follows.

When the transmitting module 10 transmits data at the rising edge of the clock applied from the receiving module 20, the corresponding data is applied to the data correction circuit 30 via the transmission path and input to the first delay circuit 31. do. At this time, the first delay circuit 31 delays the data applied from the transmission module 10 by a half cycle of the clock according to the frame synchronization signal FS and the clock, and outputs the delayed data to the second delay circuit 32 side. Thereafter, the second delay circuit 32 outputs the received corresponding data to the receiving module 20 by delaying 15 times the clock according to the frame synchronizing signal FS and the clock. Accordingly, since the data applied to the receiving module 20 has a minimum data hold time, the receiving module 20 receives the corresponding data without loss.

That is, as shown in FIG. 6, when the transmitting module 10 transmits data at the rising edge of the clock, when the first delay circuit 31 delays the corresponding transmission data by a half cycle of the clock and outputs the transmission path, The minimum data hold time is ensured. If the data is delayed only by a half cycle of the clock, the receiving module 20 cannot read the data at the rising edge 31 of the clock and reads the data at the rising edge 1 of the clock. have. Accordingly, in order for the receiving module 20 to read data at the rising edge 31 of the clock, as shown in FIG. 7, the data output from the first delay circuit 31 is output to the second delay circuit 32. By delaying by 15 cycles of the clock and outputting the data, the receiving module 20 reads data at the rising edge 31 of the clock. At this time, since the minimum hold time is maintained, the receiving module 20 reads the data without loss. It will be.

As described above, in the present invention, when the transmitting side transmits data at the rising edge of the clock and the receiving side receives the corresponding data at the rising edge of the clock, the present invention corrects the corresponding data to maintain sufficient data hold time. As a result, the receiving side receives the data without loss.

Claims (1)

A receiving module 20 for outputting a frame synchronizing signal and a clock through a transmission path and receiving data applied through the transmission path according to the clock; and a frame synchronizing signal applied through the transmission path from the receiving module 20. In the data transmission / reception system including a transmission module 10 receiving a clock and a clock and transmitting data to the receiving module 20 in accordance with the clock, the data applied from the transmitting module 10 is synchronized with the frame. A first delay circuit (31) for delaying output by a first predetermined period of the clock in accordance with a signal and a clock; A second delay circuit 32 outputting the data applied from the first delay circuit 31 to the receiving module 20 by delaying the data by the second predetermined period of the clock according to the frame synchronization signal and the clock; The data correction circuit of the data transmission / reception system according to claim 1, wherein the data hold time is maintained when data is received by the reception module.