KR980013072A - Data correction circuit of the data transmission / reception system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception system for transmitting / receiving data, and more particularly, to a data correction circuit of a data transmission / reception system for allowing a reception side to receive data without loss when data is transmitted from the transmission side. In the conventional data transmission / reception system, when the transmission side transmits data at the rising edge of the clock and the reception side receives the data applied from the transmission side at the rising edge of the clock, the minimum data hold time in the transmission path is maintained There is a problem that the receiver can not read the data correctly and is lost.

When the transmitting side transmits data at the rising edge of the clock and the receiving side receives the corresponding data at the rising edge of the clock, the data is corrected and the sufficient data hold time is maintained to be applied to the receiving side. To receive the corresponding data without loss.

Description

Data correction circuit of data transmission / reception system

The present invention relates to a data transmission / reception system for transmitting and receiving data, and more particularly, to a data correction circuit of a data transmission / reception system for allowing a reception side to receive data without loss when data is transmitted from the transmission side.

Generally, when data is transmitted / received, the data can be successfully exchanged only when the data transmitted from the transmission side can be received without loss by the receiving side.

Conventionally, when data is transmitted / received, it is transmitted / received in the manner as shown in FIG. That is, the transmitting module 10 transmits data to the receiving module 20, and transmits the data according to the frame synchronizing signal FS and the clock applied from the receiving module 20. When the transmitting module 10 transmits data to the receiving module 20, the transmitting module 10 transmits data according to the frame synchronizing signal FS and the clock as shown in FIG. 2, And the receiving module 20 receives data at the rising edge of the corresponding clock. On the other hand, when the transmission module 10 transmits data at the rising edge of the clock, since the corresponding data reaches the reception module 20 a little after the rising edge of the clock as shown in FIG. 3, Due to the fact that the hold time (about 20 ns) is not maintained, the receiving module 20 can not read valid data at the rising edge of the clock. 3, when the transmitting module 10 transmits data at the rising edge "31" of the clock, the receiving module 20 does not read from the rising edge "31" of the corresponding clock and rises The data is read from the edge "1". At this time, in order for the receiving module 20 to read data at the rising edge "1 " of the clock, a minimum data hold time must be maintained on the transmission line. Since the corresponding data hold time can not be maintained, There is a problem that it can not read.

It is an object of the present invention to provide a data correction circuit of a data transmission / reception system for allowing a reception side to receive data without loss when data is transmitted from the transmission side.

According to an aspect of the present invention, there is provided a method for controlling a clock signal, the method comprising: receiving a frame synchronizing signal and a clock through a transmission path and receiving data applied through a transmission path at a rising edge of the clock; And a transmission module for receiving a frame synchronous signal and a clock applied through the transmission line from the reception module and transmitting data to the reception module at a rising edge of the clock, the data transmission / reception system comprising: A first delay circuit for delaying data according to the frame synchronizing signal and the clock by a half period of the clock; And a second delay circuit delaying data applied from the first delay circuit by 15 periods of the clock in accordance with the frame synchronizing signal and the clock and outputting the delayed data to the receiving module side.

In the present invention, when the transmitter transmits data at the rising edge of the clock and the receiver receives the data at the rising edge of the clock, the receiver corrects the data to maintain a sufficient data hold time, Side receives the data without loss.

1 is a block diagram showing a conventional data transmission / reception system.

FIG. 2 and FIG. 3 are waveform diagrams for explaining the operation of the data transmission / reception system shown in FIG.

4 is a block diagram showing a data transmission / reception system according to the present invention;

5 is a configuration diagram of the data correction circuit shown in FIG.

6 and 7 are waveform diagrams for explaining the operation of the data correction circuit.

Description of the Related Art

10: Transmission module

20: Receiving module

30: Data correction circuit

31: first delay circuit

32: second delay circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The data transmission / reception system according to the present invention comprises a transmission module 10, a reception module 20 and a data correction circuit 30 as shown in FIG. The transmission module 10 transmits data to the reception module 20 side in accordance with the frame synchronization signal FS and the clock applied from the reception module 20 via the data correction circuit 30. [ The data correction circuit 30 transmits the frame synchronizing signal FS and the clock applied from the receiving module 20 to the transmitting module 10 and at the same time, FS and the clock to maintain the minimum data hold time so as to return to the receiving module 20 side. The receiving module 20 receives data in accordance with the frame synchronizing signal FS and the clock transmitted thereto by the transmitting module 10 itself.

On the other hand, the data correction circuit 30 includes a first delay circuit 31 and a second delay circuit 32 as shown in FIG. The first delay circuit 31 delays the data applied from the transmission module 10 according to the frame synchronizing signal FS and the clock and outputs the delayed data to the second delay circuit 32 by delaying the applied data by a half- . The second delay circuit 32 delays the data applied from the first delay circuit 31 according to the frame synchronizing signal FS and the clock and outputs the data supplied from the first delay circuit 31 to 15 And outputs it to the reception module 20 side. In this manner, the data correction circuit 30 performs delay correction of the data applied from the transmission module 10 and outputs the data to the reception module 20 side in such a manner that the minimum data hold time is maintained, It is correctly received without loss.

The thus configured data correction circuit 30 operates as follows.

When the transmission module 10 transmits data at the rising edge of the clock applied from the reception module 20, the data is applied to the data correction circuit 30 via the transmission line and input to the first delay circuit 31 do. At this time, the first delay circuit 31 delays the data applied from the transmission module 10 by the half period of the clock in accordance with the frame synchronizing signal FS and the clock, and outputs it to the second delay circuit 32 side. The second delay circuit 32 delays the corresponding data to be applied to the receiving module 20 by a period of 15 clocks in accordance with the frame synchronizing signal FS and the clock. Accordingly, since the data to be applied to the receiving module 20 is kept at a minimum data hold time, the receiving module 20 receives the data without loss.

6, when the transmission module 10 transmits data at the rising edge of the clock, when the first delay circuit 31 delays the transmission data by a half period of the clock and outputs it, The receiving module 20 can not read data at the rising edge "31" of the clock and reads the data at the rising edge "1" of the clock when the data is delayed by half the clock period. . Therefore, in order to allow the receiving module 20 to read data at the rising edge "31 " of the clock, the data outputted from the first delay circuit 31 is supplied to the second delay circuit The reception module 20 reads the data at the rising edge "31 " of the clock by delaying the clock by 15 periods of the clock to the reception module 20, It is read without loss.

As described above, according to the present invention, when the transmitting side transmits data at the rising edge of the clock and the receiving side receives the corresponding data at the rising edge of the clock, the data is corrected so that a sufficient data hold time is maintained, The receiving side receives the data without loss.

Claims (1)

A receiving module 20 for outputting a frame synchronizing signal and a clock through a transmission path and receiving data applied through a transmission path at a rising edge of the clock; And a transmission module (10) which receives a frame synchronizing signal and a clock applied from the receiving module (20) through a transmission path and transmits data to the receiving module (20) at a rising edge of the clock A first delay circuit (31) delaying data applied from the transmission module (10) by a half period of the clock in accordance with the frame synchronizing signal and the clock; And a second delay circuit (32) for delaying the data applied from the first delay circuit (31) by 15 periods of the clock according to the frame synchronizing signal and the clock and outputting the delayed data to the receiving module (20) And the data correction circuit of the data transmission / reception system. ※ Note: It is disclosed by the contents of the first application.