JPH0724832Y2 - Automatic transmission / reception switching circuit - Google Patents

Automatic transmission / reception switching circuit

Info

Publication number
JPH0724832Y2
JPH0724832Y2 JP1986130409U JP13040986U JPH0724832Y2 JP H0724832 Y2 JPH0724832 Y2 JP H0724832Y2 JP 1986130409 U JP1986130409 U JP 1986130409U JP 13040986 U JP13040986 U JP 13040986U JP H0724832 Y2 JPH0724832 Y2 JP H0724832Y2
Authority
JP
Japan
Prior art keywords
circuit
signal
transmission
reception
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1986130409U
Other languages
Japanese (ja)
Other versions
JPS6338432U (en
Inventor
英夫 高橋
等 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1986130409U priority Critical patent/JPH0724832Y2/en
Publication of JPS6338432U publication Critical patent/JPS6338432U/ja
Application granted granted Critical
Publication of JPH0724832Y2 publication Critical patent/JPH0724832Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は送受信自動切換回路に関し、特に通信制御装置
における送信と受信とを自動的に切換える送受信自動切
換回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a transmission / reception automatic switching circuit, and more particularly to a transmission / reception automatic switching circuit for automatically switching between transmission and reception in a communication control device.

〔従来の技術〕[Conventional technology]

従来、この種の送受信自動切換回路は、第3図に示すよ
うに、送受信切換信号VSにより、送受信の切換えを行な
うようになっていた。
Conventionally, this type of automatic transmission / reception switching circuit has been configured to switch transmission / reception by a transmission / reception switching signal V S , as shown in FIG.

この回路は、まず送信回路1aから送信データを送信する
場合ドライバ回路2を介し通信路8に送信データが出力
される。また、送信データの出力開始と同時に送受信切
換信号VSが出力され、レシーバ回路3aの動作を禁止して
送信モードとなり、送信データが受信系に入力されない
ようにする。
In this circuit, first, when transmitting data from the transmitting circuit 1a, the transmitting data is output to the communication path 8 via the driver circuit 2. Further, the transmission / reception switching signal V S is output at the same time when the output of the transmission data is started, the operation of the receiver circuit 3a is prohibited, and the transmission mode is set so that the transmission data is not input to the reception system.

また、送信完了と同時に送受信切換信号VSは受信モード
となり、レシーバ回路3aを動作可とし、通信路8を伝搬
してくる他局からの受信データの受信に備える。
At the same time as the transmission is completed, the transmission / reception switching signal V S enters the reception mode, enables the receiver circuit 3a, and prepares to receive the reception data from another station propagating through the communication path 8.

通信路8からの受信データを受信する場合は、レシーバ
回路3aを介して受信データを入力し、受信クロック生成
回路5で、例えば、この受信データのビット周期に同期
し、所定の周波数をもつクロック信号を生成し、このク
ロック信号をフリップフロップ回路6のCK端子に、レシ
ーバ回路3aの出力信号をD端子に入力してQ端子からク
ロック信号に同期した受信データを取り出し、受信回路
7へ伝達する構成となっていた。
When receiving the reception data from the communication path 8, the reception data is input via the receiver circuit 3a, and the reception clock generation circuit 5 synchronizes with the bit cycle of this reception data and has a predetermined frequency. A signal is generated, the clock signal is input to the CK terminal of the flip-flop circuit 6, the output signal of the receiver circuit 3a is input to the D terminal, and the reception data synchronized with the clock signal is extracted from the Q terminal and transmitted to the reception circuit 7. It was a composition.

〔考案が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の送受信自動切換回路は、送受信切換信号
によって送受信の切換えを行なっているので、何らかの
理由で送受信切換信号が生成できない場合、送受信の切
換えができなくなり、通信制御装置の送信及び受信が困
難になるという欠点がある。
Since the above-mentioned conventional transmission / reception automatic switching circuit switches the transmission / reception by the transmission / reception switching signal, if the transmission / reception switching signal cannot be generated for some reason, the transmission / reception cannot be switched and the transmission and reception of the communication control device is difficult. There is a drawback that

本考案の目的は、特別に送受信切換信号を生成しなくて
も送受信の自動切換えができ、通信制御装置の送信及び
受信を円滑に行うことができる送受信自動切換回路を提
供することにある。
An object of the present invention is to provide a transmission / reception automatic switching circuit that can automatically switch between transmission and reception without generating a special transmission / reception switching signal and can smoothly perform transmission and reception of a communication control device.

〔問題点を解決するための手段〕[Means for solving problems]

本考案の送受信自動切換回路は、送信時に所定の送信デ
ータを出力し、受信時に一定レベルの信号を出力する送
信回路と、通信路に対し前記送信回路の出力信号を送出
するドライバ回路と、前記通信路の信号を受信するレシ
ーバ回路と、前記送信回路の出力信号と前記レシーバ回
路の出力信号との排他的論理和をとる排他的論理和回路
と、この排他的論理和回路の出力信号を受け、送信時に
は前記送信データの所定の信号周期に同期した所定の周
波数のクロック信号を出力し、受信時には前記レシーバ
回路の出力信号の特定の信号周期に同期した所定の周波
数のクロック信号を出力する受信クロック生成回路と、
前記排他的論理和回路の出力信号を前記受信クロック生
成回路からのクロック信号に同期して取り込み、送信時
には一定レベルの信号を出力し、受信時には前記レシー
バ回路の出力信号と対応した信号を出力するフリップフ
ロップ回路とを有している。
The automatic transmission / reception switching circuit of the present invention includes: a transmission circuit that outputs predetermined transmission data at the time of transmission and a signal of a constant level at the time of reception; a driver circuit that transmits the output signal of the transmission circuit to a communication path; A receiver circuit that receives a signal of a communication path, an exclusive OR circuit that takes an exclusive OR of the output signal of the transmission circuit and the output signal of the receiver circuit, and the output signal of the exclusive OR circuit , A receiver outputs a clock signal of a predetermined frequency synchronized with a predetermined signal cycle of the transmission data during transmission, and outputs a clock signal of a predetermined frequency synchronized with a specific signal cycle of the output signal of the receiver circuit during reception A clock generation circuit,
The output signal of the exclusive OR circuit is fetched in synchronization with the clock signal from the reception clock generation circuit, a signal of a constant level is output during transmission, and a signal corresponding to the output signal of the receiver circuit is output during reception. And a flip-flop circuit.

〔実施例〕〔Example〕

次に、本考案の実施例について図面を参照して説明す
る。
Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本考案の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

この実施例は、通信路8に送信データを出力するための
送信回路1,ドライバ回路2、また通信路8からのデータ
を入力するためのレシーバ回路3,排他的論理和回路4,受
信クロック生成回路5,フリップフロップ回路6,および受
信回路7とを有する構成となっている。
In this embodiment, a transmitter circuit 1 for outputting transmission data to a communication path 8, a driver circuit 2, a receiver circuit 3 for inputting data from the communication path 8, an exclusive OR circuit 4, and a reception clock generation. It has a configuration including a circuit 5, a flip-flop circuit 6, and a receiving circuit 7.

次に、この実施例の動作について説明する。Next, the operation of this embodiment will be described.

第2図はこの実施例を動作させたときの信号の波形図で
ある。
FIG. 2 is a waveform diagram of signals when this embodiment is operated.

送信回路1から送信データVTを送信する場合(送信
時)、ドライバ回路2を介して通信路8に送信データが
出力される。その時、排他的論理和回路4の片方の一方
の入力端には、送信回路1から直接送信データVTが、も
う一方の入力端にはドライバ回路2,通信路8及びレシー
バ回路3を介して信号VIが入力される。この信号VIは、
ドライバ回路2,レシーバ回路3を経由するため、送信デ
ータVTよりも遅延して入力され、排他的論理和回路4の
出力信号VXはハザードVHが発生する波形となる。
When transmitting the transmission data V T from the transmission circuit 1 (during transmission), the transmission data is output to the communication path 8 via the driver circuit 2. At that time, the transmission data V T directly from the transmission circuit 1 is input to one of the input ends of the exclusive OR circuit 4, and the driver data 2, the communication path 8 and the receiver circuit 3 are input to the other input end. The signal V I is input. This signal V I is
Since it passes through the driver circuit 2 and the receiver circuit 3, it is input later than the transmission data V T , and the output signal V X of the exclusive OR circuit 4 has a waveform in which the hazard V H is generated.

受信クロック生成回路5は、このハザードの周期、即ち
送信データVTのビット周期に同期し、所定の周波数をも
つクロック信号VCKを発生し、このクロック信号VCKをフ
リップフロップ回路6のCK端子に入力し、D端子に入力
されるハザードVHを除去すると共に端子を高レベルに
し、送信データが受信回路7へ入力されることを禁止す
る。
The reception clock generation circuit 5 generates a clock signal V CK having a predetermined frequency in synchronization with this hazard period, that is, the bit period of the transmission data V T , and outputs this clock signal V CK to the CK terminal of the flip-flop circuit 6. To remove the hazard V H input to the D terminal and set the terminal to a high level to inhibit transmission data from being input to the receiving circuit 7.

次に、通信路8から受信データを入力する場合は(受信
時)、まずレシーバ回路3を介して受信データが入力さ
れる。
Next, when receiving the reception data from the communication path 8 (during reception), first, the reception data is input via the receiver circuit 3.

その時、排他的論理和回路4の片方の入力端には、送信
回路1の出力信号VTが受信モードを示す高レベル一定の
信号が入力されるので、レシーバ回路3の出力信号VI
排他的論理和回路4で反転され、出力信号VXとなる。
At that time, the output signal V T of the transmission circuit 1 is input to one of the input terminals of the exclusive OR circuit 4 at a constant high level indicating the reception mode, so that the output signal V I of the receiver circuit 3 is exclusive. It is inverted by the logical OR circuit 4 and becomes the output signal V X.

受信クロック生成回路5はこの出力信号VXを入力し、こ
の出力信号VXに含まれる受信データのビット周期に同期
し、所定の周波数をもつクロック信号VCKを発生し、こ
のクロック信号VCKをフリッフフロップ回路6のCK端子
に入力し、D端子に入力される出力信号VXに含まれてい
る受信データを、クロック信号VCKに同期して端子か
ら取り出し、元の受信データよりわずかに遅延した受信
データVRとして受信回路7へ伝達する。
Receiving clock generating circuit 5 inputs the output signal V X, synchronized with the bit period of the received data included in the output signal V X, generates a clock signal V CK having a predetermined frequency, the clock signal V CK Is input to the CK terminal of the flip-flop circuit 6, and the reception data included in the output signal V X input to the D terminal is extracted from the terminal in synchronization with the clock signal V CK, and is slightly smaller than the original reception data. And is transmitted to the receiving circuit 7 as the received data V R which is delayed.

従って、送受信切換信号を生成することなく、送信回路
1の出力信号VTの送信時の波形と受信時の波形を利用す
ることにより送受信の自動切換えができ、送受信が円滑
に行なわれる。
Therefore, the transmission / reception can be automatically switched by utilizing the waveform at the time of transmission and the waveform at the time of reception of the output signal V T of the transmission circuit 1 without generating the transmission / reception switching signal, and the transmission / reception is smoothly performed.

〔考案の効果〕[Effect of device]

以上説明したように本考案は、送信回路の出力信号を送
信時には送信データとし受信時には一定レベルの信号と
し、この送信回路の出力信号とレシーバ回路を通して入
力される通信路の信号との排他的論理和をとる排他的論
理和回路を設け、この排他的論理和回路の出力信号によ
りクロック信号を生成し、このクロック信号に同期して
排他的論理和回路の出力信号を取り込み、送信時には一
定レベルの信号を、受信時には通信路の信号と対応した
信号を内部回路へ伝達する構成としたので、特別に送受
信切換信号を生成しなくても送受信の自動切換が可能と
なり、通信制御装置の送信及び受信を円滑に行うことが
できる効果がある。
As described above, according to the present invention, the output signal of the transmission circuit is the transmission data at the time of transmission and the signal of the constant level is at the time of reception, and the exclusive logic between the output signal of this transmission circuit and the signal of the communication path input through the receiver circuit. An exclusive-OR circuit that takes the sum is provided, a clock signal is generated by the output signal of this exclusive-OR circuit, the output signal of the exclusive-OR circuit is fetched in synchronization with this clock signal, and at a certain level during transmission. Since the signal corresponding to the signal of the communication path is transmitted to the internal circuit at the time of reception, it is possible to automatically switch between transmission and reception without generating a special transmission / reception switching signal. There is an effect that can be done smoothly.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の一実施例を示すブロック図、第2図は
第1図に示された実施例を動作させたときの信号の波形
図、第3図は従来の送受信自動切換回路の一例を示すブ
ロック図である。 1,1a……送信回路、2……ドライバ回路、3,3a……レシ
ーバ回路、4……排他的論理和回路、5……受信クロッ
ク生成回路、6……フリップフロップ回路、7……受信
回路、8……通信路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of signals when the embodiment shown in FIG. 1 is operated, and FIG. 3 is a conventional transmission / reception automatic switching circuit. It is a block diagram which shows an example. 1,1a ... Transmitting circuit, 2 ... Driver circuit, 3,3a ... Receiver circuit, 4 ... Exclusive OR circuit, 5 ... Reception clock generation circuit, 6 ... Flip-flop circuit, 7 ... Reception Circuit, 8 ... Communication path.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】送信時に所定の送信データを出力し、受信
時に一定レベルの信号を出力する送信回路と、通信路に
対し前記送信回路の出力信号を送出するドライバ回路
と、前記通信路の信号を受信するレシーバ回路と、前記
送信回路の出力信号と前記レシーバ回路の出力信号との
排他的論理和をとる排他的論理和回路と、この排他的論
理和回路の出力信号を受け、送信時には前記送信データ
の所定の信号周期に同期した所定の周波数のクロック信
号を出力し、受信時には前記レシーバ回路の出力信号の
特定の信号周期に同期した所定の周波数のクロック信号
を出力する受信クロック生成回路と、前記排他的論理和
回路の出力信号を前記受信クロック生成回路からのクロ
ック信号に同期して取り込み、送信時には一定レベルの
信号を出力し、受信時には前記レシーバ回路の出力信号
と対応した信号を出力するフリップフロップ回路とを有
することを特徴とする送受信自動切換回路。
1. A transmission circuit which outputs predetermined transmission data at the time of transmission and outputs a signal of a constant level at the time of reception, a driver circuit which transmits an output signal of the transmission circuit to a communication path, and a signal of the communication path. A receiver circuit for receiving, an exclusive OR circuit that takes an exclusive OR of the output signal of the transmitter circuit and the output signal of the receiver circuit, and an output signal of the exclusive OR circuit, A reception clock generation circuit that outputs a clock signal of a predetermined frequency that is synchronized with a predetermined signal period of transmission data, and outputs a clock signal of a predetermined frequency that is synchronized with a specific signal period of the output signal of the receiver circuit when receiving; , The output signal of the exclusive OR circuit is fetched in synchronization with the clock signal from the reception clock generation circuit, and a signal of a constant level is output during transmission and reception Receive automatic switching circuit, characterized in that it comprises a flip-flop circuit for outputting a signal corresponding to the output signal of the receiver circuit is.
JP1986130409U 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit Expired - Lifetime JPH0724832Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986130409U JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986130409U JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Publications (2)

Publication Number Publication Date
JPS6338432U JPS6338432U (en) 1988-03-12
JPH0724832Y2 true JPH0724832Y2 (en) 1995-06-05

Family

ID=31027880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986130409U Expired - Lifetime JPH0724832Y2 (en) 1986-08-26 1986-08-26 Automatic transmission / reception switching circuit

Country Status (1)

Country Link
JP (1) JPH0724832Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854764A (en) * 1981-09-28 1983-03-31 Nec Corp Interface circuit

Also Published As

Publication number Publication date
JPS6338432U (en) 1988-03-12

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