JPH0537588A - Communication equipment - Google Patents

Abstract

PURPOSE:To obtain the communication equipment in which synchronization communication or asynchronization communication is switched automatically. CONSTITUTION:A communication equipment 1 is provided with a connector section 10 connecting to a communication opposite party, a communication control circuit 20 sending/receiving a data, a CPU 30 connecting to the communication control circuit 20, a clock generating circuit 40 generating an internal clock for the operation of the entire equipment together with the CPU 30, and a clock discrimination circuit 50 discriminating whether or not a clock signal for transmission reception is sent from the communication opposite party. When the clock signal is sent from the communication opposite party, the CPU 30 inputs the clock signal to the communication control circuit 20 and inputs an internal clock from the clock generating circuit 40 to the communication control circuit 20 when no clock signal is sent from the communication opposite party to activate the communication control circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device provided with a communication control unit which operates by a clock signal input from the outside and transmits / receives data.

[0002]

2. Description of the Related Art In general communication, in order to accurately transmit and receive data, synchronous communication for transmitting and receiving data based on a clock signal transmitted from a communication partner side and the clock signal from the communication partner side are not used. , Asynchronous communication in which data is transmitted and received based on an internal clock signal of the communication device.

In such a conventional communication device,
In order to deal with these two communication methods, a model equipped with a circuit for receiving a clock signal from a communication partner for synchronous communication and a model equipped with a circuit for generating an internal clock signal for asynchronous communication are provided. Prepare different types of models,
Alternatively, a switch for synchronous / asynchronous switching is provided outside the device equipped with the circuits of both models and both circuits are switched by the switch.

[0004]

However, in such a conventional technique, either synchronous or asynchronous is determined in advance and a model used for communication is selected or an external switch is switched. It was necessary to put it in, and it was very troublesome to select such a model and switch.

Further, in the conventional technique, synchronization and
Since communication is performed by deciding asynchronism and selecting the system configuration for any of the communication methods, for example, in synchronous communication, if the clock signal is not sent from the communication partner due to trouble etc., communication is impossible Fell into.

Therefore, the present invention was created for the purpose of providing a communication device capable of automatically judging whether or not a clock signal is sent from the other end of communication and coping therewith.

[0007]

Such a communication device according to the present invention is a communication device having a communication control unit for transmitting and receiving data by a clock signal input from the outside, as illustrated in FIG. An external clock input terminal for receiving a clock signal from the communication partner side, a determination means for determining whether or not the clock signal from the communication partner side is input to the external clock input terminal, and the communication control unit Internal clock generation means for generating a clock signal for transmitting and receiving, and based on the determination result of the determination means,
When the clock signal from the communication partner is input to the external clock input terminal, the clock signal is input to the communication control unit, and the clock signal from the communication partner is input to the external clock input terminal. If not, clock signal switching means for inputting the clock signal generated by the internal clock generating means to the communication control section,
It is characterized by having.

[0008]

In the communication device according to the present invention having such a configuration, first, the determining means determines whether or not the clock signal from the communication partner side is input to the external clock input terminal. judge. Then, when the clock signal from the communication partner is input to the external clock input terminal based on the determination result of the determination unit, the clock signal switching unit inputs the clock signal to the communication control unit and the external clock is input. When the clock signal from the communication partner is not input to the input terminal, the clock signal generated by the internal clock generation means is input to the communication control unit.

Therefore, according to the present invention, the communication system is synchronized with the communication method based on the judgment result of the judgment means in both cases where the clock signal is sent from the communication partner side and not sent. It is possible to automatically switch to either asynchronous communication, and it is very convenient because it is not necessary to change the model or switch the external switch to support either synchronous communication or asynchronous communication as in the past. is there.

Further, it is economical because it is not necessary to prepare two kinds of devices having different specifications or to provide a special changeover switch, an input / output unit and the like as in the conventional case. Further, according to the present invention, when the clock signal is not sent from the communication partner side, the data is transmitted and received by the clock signal generated by the internal clock generation means based on the determination result of the determination means. If a clock signal is not sent from the other party due to a trouble, etc., the communication will not be lost.

[0011]

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the examples described in detail below, and includes all examples that can be conceived by those skilled in the art without departing from the gist of the present invention.

The first embodiment shown in FIG. 1 to FIG.
Communication device 1 having serial interface of 232C
Is. The communication device 1 according to the first embodiment includes a RS232C connector unit 10 (only the main pins are shown) for connecting to a communication partner side that transmits and receives data, and a communication control circuit 20 that controls the transmission and reception of data. , A central processing unit (CPU) 30, which is connected to the communication control circuit 20, processes data transmitted and received, and controls the communication control circuit 20, etc.
Input / output device 33 and storage device 3 connected to U30
7. From a clock generation circuit 40 that creates an internal clock signal for the operation of the entire device including the CPU 30, and a clock determination circuit 50 that determines whether or not a transmission / reception clock signal is sent from the communication partner. It is configured.

The connector section 10 has an SD pin 103 for sending a data signal to the communication partner, an RD pin 104 for receiving the data signal sent from the communication partner, and a clock signal for sending the data signal. ST2 pin 114 received from the communication partner, and R for receiving the clock signal for receiving the data signal from the communication partner
It has a T-pin 115.

That is, in the case of synchronous communication, ST2 pin 1
A clock signal is input from the communication partner via 14 and the communication device 1 transmits a data signal to the communication partner in synchronization with the communication partner based on the clock signal. Also, a clock signal from the communication partner is input via the RT pin 115, and the communication device 1 receives the data signal sent from the communication partner while synchronizing with the communication partner based on the clock signal.

The communication control circuit 20 for processing these data signals and clock signals to perform data communication includes a buffer circuit, a serial / parallel conversion circuit, a read / write control circuit, a transmission control circuit, a reception control circuit, and an interface. It has a well-known structure including a circuit and the like.

The CPU 30 connected to the communication control circuit 20 and the clock generation circuit 40 for generating an internal clock signal for the entire communication device 1 are also well-known structures. Further, the clock determination circuit 50 connected to the CPU 30, the ST2 pin 114, and the RT pin 115, respectively.
Includes a clock discrimination circuit 51 having the structure shown in FIG.

That is, in the clock discrimination circuit 51, the cathode of the diode 53 is connected to the ST2 pin 114 or the RT pin 115, and the anode of the diode 53 is connected to the input terminal of the inverter 55 having hysteresis via the resistor R1. The output terminal of the inverter 55 is connected to the CPU 30. A bias power supply E1 via a resistor R0 and a capacitor C1 inserted between the resistor 53 and the ground are connected between the anode of the diode 53 and the resistor R1, and a contact point V1 is formed at the connection point. ing.

The clock discriminating circuit 5 thus constructed.
1, the capacitor C by the power source E1 is supplied only while the clock signal as shown in FIG.
1 is repeated, the contact V1 is kept at a high potential, the output of the inverter 55 is at a low level, and the contact V1 is kept at a low potential when no clock signal is input. The output becomes Hi level (FIG. 2 (b)).

In the clock determination circuit 50 having such a clock determination circuit 51, it is determined whether or not each of the ST2 pin 114 and the RT pin 115 receives the clock signal from the communication partner side.
As described above with respect to 115, it is sent to the CPU 30 as an output signal of Low level when receiving the clock signal and Hi level when not receiving the clock signal.

The CPU 30 has the clock determination circuit 50.
When an external clock signal sent from the other party is used as a clock signal for sending and receiving data based on the signal from (the synchronous communication), the internal clock signal for the system is divided and the clock signal is generated. Switching between creating and using (asynchronous communication).

An initial setting procedure for automatically selecting either synchronous or asynchronous based on the output signal from the clock determination circuit 50 will be described below. First, as shown in FIG. 3, the CPU 30 reads the output of the clock determination circuit 50 (STEP 1) and determines whether the output is Hi or Low (STEP 3). When the output is Low, the external clock signal sent from the other party of communication is selected (ST
EP5), a command to that effect is sent from the CPU 30 to the communication control circuit 20, and communication processing based on the synchronous communication system is started.

When the output of the clock determination circuit 50 is Hi in step 3, a value corresponding to the communication speed is written to the counter in the communication control circuit 20 according to a command from the CPU 30, and the counter value of the internal clock signal is set (ST.
EP7). By setting this counter value,
The internal clock signal is frequency-divided according to the communication speed, so that data can be transmitted / received accurately according to the communication speed. And the CPU 30
When a command to turn on the internal clock is issued from the communication control circuit 20 (STEP 9), communication processing by an asynchronous communication system based on the internal clock signal divided based on the clock signal generated by the clock generation circuit 40 is started. .

Such initial setting is always performed before a series of communication processes, and either synchronous or asynchronous in data communication is automatically selected. By using the first embodiment as described in detail above, one communication device can automatically cope with both synchronous communication and asynchronous communication methods. There is no need to change the device or switch the switch accordingly, which is simple. Further, it is economical because it is not necessary to prepare two kinds of devices having different specifications or to provide a special changeover switch, an input / output unit, or the like corresponding to the communication system.

Further, when the clock signal is not transmitted from the communication partner side, data is transmitted and received based on the internal clock signal, so that the clock signal is not transmitted due to troubles occurring during the synchronous communication. However, there is no possibility of communication failure.

Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, in the synchronous communication system, even when the clock signal is not sent from the communication partner due to a trouble or the like, an internal clock signal is generated based on the clock signal included in the transmission data, and the internal clock signal is used as the clock signal. It is the communication device 2 for transmitting and receiving data based on the communication partner side. The structure of the communication device 2 is substantially the same as the structure of the first embodiment described above with a specific structure added thereto. Therefore, the same parts as those of the first embodiment are shown in FIG. The same reference numerals as those in FIG. 4 are given in FIG. 4, and the description is omitted.

The communication device 2 of the second embodiment further includes a clock generation circuit 80 in addition to the clock generation circuit 40 of the first embodiment. Clock generation circuit 80
Generates a clock signal dedicated to communication control based on a data signal, and does not generate an internal clock signal of the entire system unlike the clock generation circuit 40. The clock generation circuit 80 is the communication control circuit 20.
It is also connected to the CPU 30 and to the RD pin 104 that receives a data signal from the communication partner.

As the clock generation circuit 80, specifically, a digital phase synchronization circuit (DPLL) as shown in FIG.
81 is used. The DPLL 81 includes an edge detection circuit 83,
It is composed of a 5-bit counter 85 and a decoder 87. The edge of the received data signal received by the RD pin 104 is detected by the edge detection circuit 83, the phase is corrected by the 5-bit counter 85 under the control of the CPU 30, and the received clock signal and / or transmission is performed from the decoders 87, 87. The clock signal is sent to the communication control circuit 20.

Also in the second embodiment, as in the first embodiment, when the output of the clock determination circuit 50 is Hi, that is, the clock signal for transmission or reception from the communication partner side is the ST2 pin 114 or RT. When it is not sent through the pin 115, the clock generation circuit 80 operates based on a command from the CPU 30, and for communication control based on the data signal sent from the communication partner side through the RD pin 104. The internal clock signal is generated, and the communication device 2 can perform synchronous communication with the communication partner based on the internal clock signal.

Therefore, according to the second embodiment, in the synchronous communication, even if the clock signal from the communication partner is cut off for some reason, it is created based on the data signal from the communication partner. It is possible to continue the synchronous communication based on the internal clock signal.

As described above, as an embodiment of the present invention, RS232
Although the communication devices 1 and 2 provided with the C serial interface have been described, the present invention is not limited thereto, and the present invention can be applied to a communication device provided with another interface. Further, it can be applied not only to the communication by the electric signal as in the above embodiment but also to the optical communication and other communication. Further, the present invention can be applied to not only the wired communication as in the above embodiment but also the wireless communication.

In addition, the clock discriminating circuit 51 or the DPLL 81 described in the embodiments is merely an example, and instead of them, a device capable of judging whether or not a clock signal is sent, or a communication partner. Any device can be used as long as it can generate a clock signal based on a data signal from the side.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is an explanatory diagram of a clock discrimination circuit 51.

FIG. 3 is a flowchart for initial setting of communication control using the first embodiment.

FIG. 4 is a block diagram of a second embodiment.

5 is a block diagram of a clock generation circuit 80. FIG.

FIG. 6 is a claim correspondence diagram illustrating the configuration of the present invention.

[Explanation of symbols]

1, 2 ... communication device 10 ... connector part,
20 ... Communication control unit, 30 ... CPU, 40
... clock generation circuit, 50 ... determination circuit, 80 ... clock generation circuit, 104 ... RD pin, 114 ... S
T2 pin, 115 ... RT pin,

Claims (1)

Claim: What is claimed is: 1. A communication device comprising a communication control unit for transmitting and receiving data according to a clock signal input from the outside, the external clock input terminal receiving a clock signal from a communication partner side, Determination means for determining whether or not a clock signal from a communication partner is input to the external clock input terminal; internal clock generation means for generating a clock signal for the communication control unit to transmit and receive data; Based on the determination result of the determination means, when the clock signal from the communication partner is input to the external clock input terminal, the clock signal is input to the communication control unit and the communication partner is input to the external clock input terminal. When the clock signal from the side is not input, the clock signal generated by the internal clock generation means is input to the communication control unit. Communication apparatus characterized by comprising: a clock signal switching means, a to.