JPS59194550A - Testing circuit of line adaptor - Google Patents

Abstract

PURPOSE:To break whether a transmission part or a receiving part is abnormal and to shorten the time required for the search of a fault or repairment of a failure by changing write data in a read/write memory and testing only receiving operation. CONSTITUTION:The read/write memory 46 having one-bit data width can be preset to an optional value from a communication control device 3 and also can be written from the device 3 addressed by an address counter 45 counted up by a testing clock signal. A selector 47 selects data read out from the memory 46 are receiving data to a receiving part in a transmission/reception control circuit 21 in stead of data received from a communication line through a line interface circuit 40. Therefore, the abnormality of the transmission part can be broken from that of the receiving part by changing data to be written in the memory 46 and testing only the receiving operation of various data patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an adapter that is provided at a terminal of a data communication circuit and used by being inserted into a communication line. 1. Particularly regarding the test circuit in a single-channel adapter [Description of Prior Art] FIG. 1 is a block diagram of a line attack equipped with a conventional test circuit. The prior art will be explained with reference to FIG.

2 is a communication control device of a data communication terminal, and an adapter 2 is inserted into the communication circuit of this communication control device. Test instructions from communication control device 1 Upper interface circuit 20
In response, it outputs a test instruction signal 205 to the first selector 22 . With this signal, the first selector 22 logically disconnects the transmission/reception control circuit 21 and line interface circuit 23, returns the transmission data signal 203 to the reception data signal 201, and clocks the transmission timing signal 204 and reception timing signal 202. The signal is supplied from the generating circuit 24.

When the communication control device 1 completes the logical connection for the test shown above, it sends a transmission data signal in units of characters to the transmission and reception control circuit 21 via the upper level interface circuit 20, and the transmission unit in the transmission and reception control circuit 21 outputs the above transmission character as a bit series transmission data signal 203 using a transmission timing signal 204. The first selector 22 selects the transmitted data signal 203 from the received data signal 201.
Then, the receiving section in the transmission/reception control circuit 21 receives the bit serial reception data signal 201 in accordance with the reception timing signal 202. This is assembled into a character and sent to the communication control device 1 via the upper level interface circuit 20. The communication control device 1 then tests the line adapter 2 by comparing the transmitted characters with the received characters and characters from the line adapter 2.

Therefore, this type of conventional test method has the disadvantage that if the comparison results between the transmitted character and the received character do not match, it cannot be determined whether the reception operation of the line adapter 2 is abnormal or the transmission operation is abnormal. there were.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a test circuit for a line adapter which can perform an independent test of only the receiving operation and separately detect abnormalities in the transmitting operation and abnormalities in the receiving operation.

[Key points of Zuf Ming]

The test circuit for the line adapter of the present invention, in addition to the test circuit for converting the transmission data of the conventional recuperation adapter into the reception data, can be preset to any value from the communication control device and can be counted up by the test clock signal. an address counter addressed by the address counter and having a data width of 1 bit that can be accessed from the communication control device via a higher-level interface circuit; This test circuit also includes a circuit including a second selector that outputs read data from the write memory as a reception data signal to a receiving section in the transmission/reception control circuit.

Write the test data to the read/write memory in advance,
After that, when the test is started, the contents of the read/write memory are sequentially read out and sent to the receiving section in the transmitting/receiving circuit via the second selector, where they are assembled into received characters in the transmitting/receiving control circuit and transferred to the communication control device. . The communication control device compares the test data written in the read/write memory with the transferred received character, and if there is an abnormality, it is regarded as an abnormality in the receiving operation of the line adapter. If it is normal, a test is performed in which the transmission data from the transmitter in the transmitter/receiver control circuit is looped back as received data to the receiver in the transmitter/receiver control circuit via the first selector, and if it is abnormal, the transmission operation of the line adapter is performed. The present invention is characterized in that it is possible to determine whether the receiving operation or the transmitting operation of the line adapter is abnormal by determining that the line adapter is abnormal.

[Explanation based on an embodiment] FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention.This embodiment circuit has an address counter 45, a read/write memory 46, and a second selector 47 added to the conventional test circuit. The upper level interface circuit 40 and the communication control device 3
is unique in that it has been modified in line with the additions mentioned above.

The address counter 45 receives an address set information signal 4 from the communication control device 3 via the manual interface circuit 40.
11 is configured to be set to an arbitrary value, and when the communication control device 3 instructs a test by the receiver test instruction signal 410 via the host interface circuit 40, the clock generation circuit 24 It is configured to be counted up by the test clock signal 206, and to stop counting up when an overflow occurs.

The 1-bit memory 46 is a 1' bit wide memory for storing test data, and is addressed by the address signal 407 from the address counter 45.
Further, the test data is written in by the data set information signal 412 from the communication control device 3 via the host interface circuit 40.

When the second selector 47 is instructed to test the receiver by the receiver test instruction signal 410, the second selector 47 selects the first selector 2
The read data signal 40B of the read/write memory 46 is selected in place of the received data signal 201 from the transmitting/receiving control circuit 21 as the received data signal B4O9.

The operation of such a device will be explained.

When testing only the receiving section of the transmission/reception control circuit 21, the communication control device 3 reads out test data by repeatedly setting an address to the address counter 45 and writing data to the read/write memory 46. After the data is stored in the data, the reception unit in the transmission/reception control circuit 21 is permitted to operate. Thereafter, the test instruction signal 205 and the receiver test instruction signal 410 are set. The test instruction signal 205 causes the first selector 22 to control the clock generation circuit U.
The test clock signal 206 generated by the test clock signal 206 is applied to the receiver in the transmission/reception control circuit 21 as the reception timing signal 202.The receiver test instruction signal 410 also allows the address counter 45 to count up, and the address counter 45 is used for testing. It is counted up by one by the clock signal 206. The test data stored in the read/write memory 46 is sequentially read out by the address signal 407 which is the output of the counter.

The selector B47 allows the read data signal 408 of the read/write memory 46 to be heard by the receiving section in the transmission/reception control circuit 21 as a received data signal B 409. The receiving section of this transmission/reception control circuit uses the received data signal 409 as a character.
The data is set to 1 and transferred as a received character to the communication control device 3 via the upper interface circuit 40'r. ]l))
After setting the receiving unit test instruction signal 41-O, the control device 3 sets the test 1 of the 7-bit string stored in the memory 46 including the song, output ψ1 (store data and line adapter 4).
Compare the received characters transferred from 0, send/receive,
Check the operation of the receiving section of the control circuit.

If the result of the above-mentioned receiving unit test is normal, the communication control device 3 resets the receiving unit test instruction signal 410 and also allows the receiving unit in the transmission/reception control circuit 21 to operate. , a test is performed on the return of the transmission data 203 to the reception data 201 by the box selector 22. If an abnormality occurs as a result, it can be regarded as an abnormality in the circuit related to the transmission operation.

Furthermore, some failures occur only in certain data patterns. According to the test circuit of the present invention, it is possible to test only the reception operation for various data patterns by changing only the data written to the read/write memory 46.1.The first selector and the second selector are It can also be one piece of hardware.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to determine whether the transmitting section of the line adapter or the receiving section is abnormal using simple hardware.

This makes it possible to shorten the time required for fault investigation, fault repair, and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional line adapter test circuit. FIG. 2 is a block diagram showing a circuit according to an embodiment of the present invention. 1... Communication control device, 2... Conventional line adapter,
20... Upper interface circuit, 21... Transmission/reception control circuit, 22... Gloss, - selector, 23... Line interface circuit, 24... Clock generation circuit,
3... Communication control device corresponding to the present invention, 4... Line adapter of the present invention, 40... Modified upper level interface circuit, 45... Address counter, 46...
Read/write memory, 47...second selector, 20
DESCRIPTION OF SYMBOLS 1... Reception data signal, 202... Reception timing signal, 203... Transmission data signal, 204... Transmission timing signal, 205... Test instruction signal, 206...
...Test clock signal, 407...Address signal,
408... Read data signal, 409... Received data signal B, 410... Receiving unit test instruction signal, 411...
. . . Address set information signal, 412 . . . Data set information signal. Patent applicant: NEC Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] (1) IT; a host interface circuit that transfers control information to and from the i-information control device; a receiving unit that assembles the serial data of the received data signal into parallel data; and a receiver that assembles the serial data of the received data signal into serial data. A line adapter equipped with a transmission/reception control circuit including a transmitter that performs disassembly into 1 and a line interface circuit that performs electrical conversion between the communication port and the line is connected between the memo communication control device and the communication line. This line adapter includes a clock generation circuit that generates a test clock signal, and a clock generation circuit that generates a test clock signal, and a clock generation circuit that generates a test clock signal, and a clock generator that generates a test clock signal in place of the received data from the communication line via the line ink face circuit according to instructions from the control device. Transmit 1g output by the transmitter in the transmitter/receiver control circuit
In a test circuit for a line adapter that includes a first selector for returning data to received data to a receiving section in the transmission/reception control circuit, the test circuit can be preset to any value from the communication control device, and an address counter that is counted up by a clock signal for the communication; a read/write memory that is addressed by the address counter and has a data width of 1 bit and that is writable by the communication control device; and a second selector for making the read data of the read/write memory into the reception data to the receiving section in the transmission/reception control circuit instead of the data received from the communication line via the line interface circuit. A test circuit for a line adapter characterized by: