JPH03228455A - Automatic switching system for reference clock source - Google Patents

Abstract

PURPOSE:To eliminate the system-down state of a CPU and to reduce the processing load by constituting the system so that a fault in a clock source device, and a power source disconnection fault, etc., are detected by a non- reference clock source device, and the next high number device of a reference clock source device becomes automatically a reference clock source. CONSTITUTION:The system is provided with a device number recognizing circuit 3 for recognizing and holding what ordinal number device from a reference clock source device the device itself is from a time slot difference between a frame head signal and a sub-frame head signal received from a low number device to each device, and a fault detecting circuit for detecting fault information of the low number device from the inside of each device and its device and sending it out to a high number device. Also, this system is provided with a clock/frame generating circuit 1 for generating a frame head signal and a sub-frame head signal, and a fundamental clock by information from the device number recognizing circuit 3 and the fault detecting circuit 4, and a clock source control circuit 2 for controlling it. In such a way, the reference clock source is switched automatically without executing the software processing of a CPU and the load of the CPU is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to electronic exchanges, and more particularly to an automatic reference clock source switching method for a common bus control method for a system comprising a plurality of devices.

2. Description of the Related Art Conventionally, as shown in FIG. 4, a switching method for a reference clock source device in a common bus of this type is based on a clock and frame head signal system circuit in a device that is a reference clock source and a turning point of a common bus. When a failure occurs, the central control unit (CPU) recognizes the failure information and newly sets the reference clock source device.

Problems to be Solved by the Invention Since the above-mentioned conventional system is executed by software processing of the CPU, if the reference clock source device becomes inoperable due to a device power failure or clock interruption, etc.
It takes a considerable amount of time for the CPU to detect a failure and make new settings, resulting in a prolonged system down state.

Furthermore, in order to shorten the time during which the system is down, it is necessary to shorten the regular failure inspection cycle of the CPU, which has the drawback of significantly reducing the processing capacity of the CPU.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel reference clock source automatic switching system that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the reference clock source automatic switching system according to the present invention transfers data to a device consisting of n devices from No. 1 to No. n. Data is counted from the transmission bus and the device with the lower number to the device with the higher number, and based on the time slot difference, the device itself determines the number of devices connected to the reference clock source device, and each device receives data from the device with the lower number. The time slot on the common bus is recognized based on the frame head signal and the basic clock signal received from the frame head signal and a delay of one time slot for each bag, and the data inside each device and the device with a lower number than that device is recognized. are punched (counted) for each device using an internal clock created from the basic clock, and the electronic clocks that operate on the internal clock created from the basic clock from each device and the lower number device and constitute the common bus. In the exchange, each device uses the frame head signal, subframe head signal, and basic clock to punch out (count) the frame head signal, subframe head signal, and basic clock, and determines whether the device itself is the reference clock source based on the time slot difference. CLK and FH creation circuits that recognize the number of devices from the device and create security, and the inside of each device and its equipment! a fault detection circuit that detects fault information of a device with a lower number and sends the fault information to a device with a higher number; The device includes a clock and frame head generation circuit that generates a clock, and a clock source control circuit that controls the clock and frame head generation circuit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a detailed block diagram of the circuit components of each device shown in FIG. 1, and FIG. 3 is an operation timing chart of FIG. 1.

Referring to FIG. 1, device #1 is set in advance as a reference clock source device, and the CLK of device #1,
The reference clock CLK, frame head FH, and subframe head SFH signals created by the FH creation circuit 1 are supplied to each device #2 to #n via the driver, receiver circuit, and latch circuit between each device. There is. Then, in each device #1 to #n, a frequency dividing circuit 6 generates internal clocks CLKO to CLKn, and data latch circuits 7 for reception bus A and transmission bus B, which are common buses between the devices, are created. .8 to operate. Furthermore, device #1 controls a loopback circuit 5 that loops back data on each bus for receiving and transmitting the common bus. That is, the CLK and FH generation circuit 1 and the loopback circuit 5 are operating only in device #1 that is set as the reference clock source device, and are inactive in other devices #2 to #n (receiving data bus A
and the transmission data bus B is indicated by a broken line).

FIG. 2 shows the CLK and FH generation circuit 1 in each device. 2 is a detailed block configuration diagram of each circuit: a reference clock control circuit 2, a device number recognition circuit 3, and a failure detection circuit 4. FIG.

Referring to FIG. 2, the gate circuit 12 in the CLK and FH generation circuit 1 of device #1 is connected to the control circuit 21 in the reference clock source control circuit 2 via a line 120, and is connected to the external interface circuit. A line 220 and a line 212 connected to 22 are preset as a reference clock source for generating CLK, FH, and SFH signals.

At this time, the oscillation circuit 10 of the CLK and FH generation circuit 1 is connected by lines 110 and 122 to an FH generation circuit 11 constituted by, for example, a counter and a gate circuit 12, respectively, and supplies the CLK. FH creation circuit 11
sends frame head and subframe head signals FH and SFH to device #1 to device #2 via the gate circuit 12 at the timing shown in FIG. 3 based on the received clock CLK.

In device #2, the frame head and subframe head signals FH and SFH having the timing shown in FIG.
The difference is input to a difference detection circuit 30 constituted by a counter, for example, in the device number recognition circuit 3 connected to lines 302 and 301, and the difference is detected there by an internal clock divided by a frequency dividing circuit 6 connected to line 302. and the difference is line 3
10, and is input into a holding circuit 31 formed of, for example, an F/F, and is held there.

In the reference clock source control circuit 2, the data from the holding circuit 31 is connected via a line 200 to a determination circuit 20 constituted by a comparator, for example, and it is determined whether or not it is the next reference clock source device. If it is a reference clock source, it sends a signal on line 211.

The control circuit 21 receives the lower number device failure information outputted from the power system failure detection circuit 40 configured by, for example, a comparator in the lower number device failure detection circuit 4 and inputted to the signal line 210 of the higher number device; For example, a clock composed of a comparator +
The input CLK, FH, and SFH disconnection information from the lower number device detected by the FH system failure detection circuit 41 is received via the line 213. Then, based on the determination result and fault information detected by the determination circuit 20 described above, the gate circuit 12 in the CLK and FH generation circuit 1 is controlled, and at the same time, the return circuit 5 of the common bus is controlled by the line 500. As a result, device #2
It comes to control the entire system as a reference clock source device. Devices #3 to #n operate similarly.

For fault detection, Tarokku F) (system fault detection circuit 4
1 detects the disconnection of the clock CLK and frame head FH signals inputted from the lower number device via the lines 410, 411, and 412, and the power supply failure detection circuit 40 detects the disconnection of the power of the own device. And that information is sent to the CPU at the same time.
It is sent to the interface circuit 42 via lines 210, 213. Also, a line 420 connects the CPU to the CPU.
The interface circuit 42 sends out the information, and the power system failure detection circuit 40 sends the information to the older number device using a line 401 connected to the line 210 of the older number device.

The faulty operation of device #2 in FIG. 3 is shown in the timing chart described above. At this time, device #2 receives frame head and subframe head signals F)1. By making the difference in SFH the same as the difference in device #1 before the failure, device #3 becomes device #2 before the failure, and the normal operation of the common bus is maintained.

Then, at the stage when the fault in device #1 before the fault has been cleared, the fault detection circuit 4 sends the fault clearing message to the control circuit, so that the control circuit resets device #1 to become the reference clock source device. I do.

As described in detail, according to the present invention, a non-reference clock source device can detect CLK and FH signal failures in a reference clock source device that is set to an initial state in advance, or a power-off failure of that device. By detecting this and automatically making the device with the highest number next to the reference clock source device the reference clock source, it is possible to eliminate a system down state in which the common bus is temporarily unavailable without the intervention of the CPU. Moreover, the effect of reducing the processing load on the CPU can be obtained.

[Brief explanation of drawings]

FIG. 1 is an overall block configuration diagram showing an embodiment of the present invention;
FIG. 2 is a detailed block diagram of each part in the apparatus shown in FIG. 1, FIG. 3 is a timing chart showing an example of the operation of the present invention, and FIG. 4 is an overall block diagram showing a conventional example. 1... CL, FH creation circuit, 2... Reference clock control circuit, 3... Equipment number recognition circuit, 4... Fault detection circuit, 5... Folding back circuit, 6... Frequency division circuit, 7
．． 8...Latch circuit, 10...Oscillation circuit, 11...
- FH creation circuit, 12... Gate circuit, 20... Judgment circuit, 21... Control circuit, 22... External interface circuit, 30... Difference detection circuit, 31... Holding circuit, 40 ...Power system fault detection circuit, 41...Clock, FH system fault detection circuit, 42...CPU interface circuit

Claims (3)

[Claims] (1) Consisting of n devices from number 1 to number n, a transmission bus that transfers data from the device with the highest number to the device with the lowest number, and a bus for reception that transfers data from the device with the lowest number to the device with the highest number. Each device is connected by a common bus that is time-divisionally controlled and the bus connects within the device with the lowest number, and each device receives a frame head signal from the device with the lowest number and is delayed by one time slot for each device. Recognizes own time slot of common bus based on subframe head signal and basic clock signal,
Further, the data on the transmission bus and the reception bus are counted for each device using an internal clock generated from the basic clock, and each device operates using the basic clock and frame head signal from the device with the lowest number. , in an electronic exchange that constitutes a common bus, if a failure occurs in any device among the n devices, the lowest numbered device connected next to the device in which the failure occurred is sent as failure information and a frame. It is automatically set as a reference clock source device based on the difference information between the head signal and the subframe head signal, and the device generates a basic clock signal, a frame head signal, and a subframe head signal to each subsequent long number device. An automatic reference clock source switching system characterized by control so that it functions as a sending and returning device. (2) Consisting of n devices from number 1 to number n, a transmission bus that transfers data from the device with the highest number to the device with the lowest number, and a reception bus that transfers data from the device with the lowest number to the device with the highest number. Each device is connected by a common bus that is time-divisionally controlled, with the bus connected within the device with the lowest number, and each device receives a frame head signal from the device with the lowest number and a delay of one time slot for each device. The self-assigned time slot of the common bus is recognized based on the subframe head signal and the basic clock signal, and the data on the transmission bus and reception bus is transferred to each device based on the basic clock signal. In an electronic exchange that counts by a clock, each device operates using the basic clock and frame head signal from the device with the lowest number, and constitutes a common bus, each device operates based on the frame head signal and subframe signal received from the device with the lowest number. A device number recognition circuit that counts the time slot difference between head signals using an internal clock of the device, recognizes and holds the device number from the reference clock source device based on the time slot difference; a fault detection circuit that detects fault information of the lower numbered device from the device and sends the fault information to the older numbered device; a CLK and FH generation circuit that creates the frame head signal, subframe head signal, and basic clock; and the device A reference clock source automatic switching system comprising: a clock source control circuit that controls the CLK and FH generation circuits based on information from a number recognition circuit and a failure detection circuit. (3) The CLK and FH generation circuit includes an oscillation circuit that generates a clock signal, an FH generation circuit that generates a frame head signal and a subframe signal using the clock signal, and an output of the FH generation circuit and the oscillation circuit. a difference detection circuit that detects the difference between the frame head signal and the subframe signal from an internal clock outputted from a frequency dividing circuit of the own device; The failure detection circuit is configured by a power system failure detection circuit that detects a power failure of its own device, and a power system failure detection circuit that detects a power failure of the device itself, and a power failure detection circuit that detects a failure of a clock signal and a frame head signal input from a lower number device. a determination circuit that determines whether the reference clock source control circuit is the next reference clock source device based on the difference held in the holding circuit; 3. The reference clock source automatic switching system according to claim 2, further comprising a control circuit that controls the gate circuit and the return circuit based on the determination result and fault information from the lower number device.