JPH0951348A - Star-type communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive star-type communication system by configurating it with one PLL circuit. SOLUTION: At the time of raising the star-type communication system, a hub switch 5 connects a hub block generation means 1 and a transmission data generation means 6, and a terminal switch 12 connects a receiver 9 and a driver 13. The PLL circuit 3 detects a phase difference D between the signal of a node A and the signal of a node C, and generates a phase advance signal 3b which advances by the phase difference D from the signal of the node C. Then, the hub switch 5 and the terminal switch 12 are respectively changed over and a mode is moved to a regular one. A hub 101 generates and transmits transmission data by the transmission data generation means 6 based on the phase advance signal 3b. Since the system can be composed of one PLL circuit, the system becomes inexpensive. Thus, the star-type communication system where a clock that a terminal clock generation means 8 outputs becomes the master clock of regular data communication at the regular communication mode is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a star communication system for communication between hubs and terminals, and more particularly to a star communication system having a simple circuit configuration.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a star type communication system in which a hub signal generated in a conventional hub is transmitted to a terminal and a terminal signal generated in the terminal is transmitted to the hub for communication. is there. First, the hub will be described. In FIG. 7, reference numeral 1 is a hub clock generating means for generating a clock 1a, 2 is a receiver for receiving a terminal signal 13a transmitted from a terminal to a hub, and 15 is a clock for receiving the clock 1a and the terminal signal 2a passed through the receiver 2. , A PLL (Phase Locked Loo) that generates a synchronization signal 15a synchronized with the terminal signal 2a.
p) circuit, 4 receives the terminal signal 2a and the synchronizing signal 15a, receives the terminal signal 2a by the synchronizing signal 15a and processes the data on the terminal signal 2a, 6 receives the clock 1a , The data transmitted to the terminal is processed at the timing of the clock 1a to generate the hub signal 6
Transmission data processing means for outputting as a, 7 is a hub signal 6
It is a driver for receiving a and transmitting the hub signal 6a to the terminal. A block 101 corresponding to each terminal is configured by the above-described components, and a hub 100 is configured by a plurality of blocks 101.

Next, the terminal will be described. Reference numeral 8 is a terminal clock generating means for generating a clock 8a, and 9 is a hub 100.
16 which receives the hub signal 7a transmitted by the
Is a PLL circuit that receives a clock 8a and a hub signal 9a that has passed through a receiver 9, and generates a synchronization signal 16a that is synchronized with the hub signal 9a. Reference numeral 10 is a hub signal 9a and a synchronization signal 16a.
In response, the hub signal 9a is taken in by the synchronizing signal 16a and the received data processing means 11 for processing the data on the hub signal 9a is received.
Transmission data processing means for processing the data to be transmitted to the terminal 8a and outputting it as the terminal signal 11a.
Reference numeral 13 denotes a driver for receiving the terminal signal 11a and transmitting the terminal signal 11a to the hub 100. The terminal 200 is composed of the above-described components. Further, 300 is between the driver 7 and the receiver 9, and driver 13 and the receiver 2.
It is a communication line that connects between each other.

Next, the operation will be described. First, hub 1
Communication from 00 to the terminal 200 will be described. The hub clock generation means 1 generates and outputs the clock 1a. The transmission data processing means 6 receives the clock 1a and outputs the hub signal 6a. The hub signal 6a is transmitted via the driver 7 to the communication line 3
00 as a hub signal 7a. Hub signal 7a
Is transmitted from the hub 100 to the terminal 200 via the communication line 300.

The receiver 9 receives the hub signal 7a and outputs it as a terminal signal 9a. The terminal clock generation means 8 generates and outputs the clock 8a. The PLL circuit 16 is
Based on the hub signal 9a and the clock 8a, the hub signal 9
a to generate a synchronization signal 16a,
To the received data processing means 10. The reception data processing means 10 uses the synchronization signal 16 which is synchronized with the hub signal 9a.
The hub signal 9a is taken in by a and the data on the hub signal 9a is processed.

The communication from the terminal 200 to the hub 100 is performed by the same operation independently of the communication from the hub 100 to the terminal 200. That is, the terminal clock generation means 8 corresponds to the operation of the hub clock generation means 1, and the transmission data processing means 11
Corresponds to the operation of the transmission data processing means 6, and the driver 13
Corresponds to the operation of the driver 7, and the receiver 2 is the receiver 9
The PLL circuit 15 corresponds to the operation of the PLL circuit 16, and the reception data processing unit 4 corresponds to the operation of the reception data processing unit 10. The terminal signal 11a corresponds to the hub signal 6a, the terminal signal 13a corresponds to the hub signal 7a, the terminal signal 2a corresponds to the hub signal 9a, and the synchronization signal 15a corresponds to the synchronization signal 16a.

[0007]

However, since the conventional star-type communication system is configured as described above, two PLL circuits 15 and 16 are required, which increases the cost of the star-type communication system. There is a problem.

The present invention has been made to solve such a problem, and an object of the present invention is to obtain an inexpensive star-type communication system by using one PLL circuit.

[0009]

The problem solving means according to claim 1 of the present invention transmits a hub signal generated in a hub to a terminal, and transmits a terminal signal generated in the terminal to the hub. It is a star type communication system that communicates by
The hub receives hub clock generating means for generating a first clock, the first clock and the terminal signal transmitted to the hub by the terminal, and a synchronization signal for synchronizing with the terminal signal and the terminal. A PLL circuit that generates a phase-advancing signal that is advanced in phase by a certain phase difference from the signal, and receives the first clock and the phase-advancing signal to receive the first clock and the phase-advancing signal. A hub switch that selects either one and outputs the hub synchronization signal, and a first switch that receives the hub synchronization signal, processes data to be transmitted to the terminal at the timing of the hub synchronization signal, and outputs the processed hub signal as the hub signal. A transmission data processing means; and a first reception data processing means for receiving the terminal signal and the synchronization signal transmitted by the terminal to the hub, and processing the terminal signal according to the synchronization signal. The terminal receives the second clock, and receives the second clock, processes the data to be transmitted to the hub at the timing of the second clock, and outputs the processed data. One of the output of the second transmission data processing means and the hub signal in response to the transmission data processing means, the output of the second transmission data processing means and the hub signal transmitted by the hub to the terminal. And a second switch that receives the hub signal transmitted to the terminal by the hub and the second clock, and processes the hub signal by the second clock. Reception data processing means, the PLL circuit selects the first clock by the hub switch, and the second transmission data processing means by the terminal switch. Detecting the phase difference between the first clock and the terminal signal at the when output as the constant phase difference.

In the problem solving means according to claim 2 of the present invention, the hub further comprises a non-volatile storage means for receiving the phase difference detected by the PLL circuit and storing the phase difference. The circuit generates the phase advance signal based on the phase difference stored in the storage means.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a diagram showing a star-type communication system that performs communication by transmitting a hub signal generated in a hub to a terminal and transmitting a terminal signal generated in the terminal to the hub according to the first embodiment of the present invention. Is. First, the structure of the hub will be described. In FIG. 1, 1 is a clock 1a
Hub clock generating means for generating (first clock),
2 is a receiver for receiving the terminal signal 13a transmitted from the terminal to the hub, 3 is the clock signal 1a and the terminal signal 2a passed through the receiver 2, and the synchronization signal 3a synchronized with the terminal signal 2a and the terminal signal 2a will be described later. The PLL circuits 4 for generating a phase-advancing signal 3b advanced in phase by the phase difference D are received by the terminal signal 2a and the synchronizing signal 3a, and the terminal signal 2a is taken in by the synchronizing signal 3a and is transferred to the terminal signal 2a. Received data processing means (first received data processing means) 5 for processing data being received receives clock 1a and phase advance signal 3b and selects either clock 1a or phase advance signal 3b to perform hub synchronization. Hub switch that outputs as signal 5a, 6
Receives the hub synchronization signal 5a, processes the data to be transmitted to the terminal at the timing of the hub synchronization signal 5a, and outputs the hub signal 6a.
A transmission data processing means (first transmission data processing means) 7 for outputting as a driver for receiving the hub signal 6a and transmitting the hub signal 6a to the terminal. A block 101 corresponding to each terminal is configured from the above-described components,
The hub 100 is composed of a plurality of blocks 101.

Next, the configuration of the terminal will be described. Reference numeral 8 is a terminal clock generating means for generating a clock 8a, 9 is a receiver for receiving the hub signal 7a transmitted from the hub 100,
10 is a hub signal 9a and a clock 8a that have passed through the receiver 9.
In response, the hub signal 9a is received by the clock 8a and the received data processing means (second received data processing means) for processing the data on the hub signal 9a is received, and 11 is received by the clock 8a and is transmitted to the hub 100. Transmission data processing means (second transmission data processing means) for processing the data to be processed at the timing of the clock 8a and outputting it as the signal 11a, 12 receives the signal 11a and the hub signal 9a, and receives the signals 11a and 9a. A terminal switch that selects either one and outputs it as the terminal signal 12a, 13 is the terminal signal 1
It is a driver that receives the terminal 2a and transmits the terminal signal 13a to the hub. The terminal 200 is composed of the above-described components.

Further, 300 is a driver 7 / receiver 9
Communication line for connecting the driver 13 and the receiver 2 respectively.

Next, the operation will be described. The operation is roughly divided into two modes. First, in the first mode,
Prepares for data communication, and the system (hub 1
00 and terminal 200) is turned on, the operation described later is performed for a certain period. In the second mode, normal data communication is performed in which the hub signal generated in the hub is transmitted to the terminal and the terminal signal generated in the terminal is transmitted to the hub. FIG. 1 shows the state of the star type communication system in the case of the first mode, and FIG. 2 shows the state of the star type communication system in the case of the second mode. Each reference numeral in FIG. 2 corresponds to each reference numeral in FIG.

First, the first mode will be described. FIG. 3 is a diagram showing the timing of each signal in the first mode. For a certain period after the power is turned on, the hub switch 5 selects the clock 1a and the terminal switch 12 selects the hub signal 9a as shown in FIG.

The hub clock generating means 1 generates and outputs the clock 1a. The hub switch 5 selects the clock 1a and outputs it as a hub synchronization signal 5a. The transmission data processing means 6 receives the hub synchronization signal 5a and outputs the data to be transmitted to the terminal 200 as the hub signal 6a at the timing of the clock 1a as shown in FIG. The hub signal 6a is output as the hub signal 7a on the communication line 300 via the driver 7. The hub signal 7a is transmitted from the hub 100 to the terminal 20.
0 via communication line 300. The receiver 9 receives the hub signal 7a and outputs it as a hub signal 9a. The terminal switch 12 selects the hub signal 9a to select the terminal signal 12a.
Output as a. At this time, as shown in FIG. 3, the hub signal is transmitted from node A in hub switch 5 to node B in terminal switch 12 with a phase delay of d1.

The terminal signal 12a is output as the terminal signal 13a on the communication line 300 via the driver 13. The terminal signal 13a is transmitted from the terminal 200 to the hub 100 via the communication line 300.
Sent via The receiver 2 receives the terminal signal 13a and outputs it as the terminal signal 2a. At this time, as shown in FIG. 3, the terminal signal is transmitted from node B to node C between receiver 2 and PLL circuit 3 with a delay of phase d2.

The PLL circuit 3 receives the terminal signal 2a and the clock 1a and receives the synchronizing signal 3a synchronized with the terminal signal 2a.
Is generated, the phase difference D (= d1 + d2) is detected by the terminal signal 2a and the clock 1a, and the phase advance signal 3 whose phase is advanced by the phase difference D (= d1 + d2) from the terminal signal 2a is generated.
Generate b. Further, in the first mode, the reception data processing means 4, 10 and the transmission data processing means 11 do not have to operate.

Next, the second mode will be described. FIG. 4 is a diagram showing the timing of each signal in the first mode. As shown in FIG. 2, the hub switch 5 selects the phase advance signal 3b, and the terminal switch 12 selects the signal 11a output by the transmission data processing means 11. In the second mode as well, the phase difference D detected in the first mode is held, and the PLL circuit 3 advances the phase by a phase difference D (= d1 + d2) from the terminal signal 2a. The phase signal 3b is generated and output.

The terminal clock generating means 8 generates and outputs the clock 8a. The transmission data processing means 11 receives the clock 8a and outputs the data to be transmitted to the terminal 100 as the signal 11a at the rising timing of the clock 8a as shown in FIG. Terminal switch 12 is signal 11a
Is selected and output as the terminal signal 12a. Terminal signal 1
2a is output as a terminal signal 13a on the communication line 300 via the driver 13. The terminal signal 13a is the terminal 200
To the hub 100 via the communication line 300. The receiver 2 receives the terminal signal 13a and outputs it as the terminal signal 2a. At this time, as shown in FIG. 4, the terminal signal is
The receiver 2 and the PLL circuit 3 are delayed from the node B by the phase d2.
Is transmitted to node C between and.

The PLL circuit 3 has a synchronization signal 3 synchronized with the terminal signal 2a based on the terminal signal 2a and the clock 1a.
a and a phase advance signal 3b having a phase advanced from the terminal signal 2a by the phase difference D obtained by detection in the first mode.
The reception data processing means 4 receives the terminal signal 2a and the synchronization signal 3a, receives the terminal signal 2a by the synchronization signal 3a, and processes the data on the terminal signal 2a. The hub switch 5 selects the phase advance signal 3b and outputs it as a hub synchronization signal 5a. At this time, as shown in FIG. 4, the phase advance signal 3b is ahead of the terminal signal 2a by the phase difference D, and therefore the phase advance signal 3b is out of phase d1 from the clock 8a.
(= D2-phase difference D).

The transmission data processing means 6 uses the hub synchronization signal 5a.
In response, the data to be transmitted to the terminal 200 is output as the hub signal 6a at the timing of the phase advance signal 3b as shown in FIG. The hub signal 6a is transmitted via the driver 7 to the communication line 3
00 as a hub signal 7a. Hub signal 7a
Is transmitted from the hub 100 to the terminal 200 via the communication line 300. The receiver 9 receives the hub signal 7a and outputs it as a hub signal 9a. At this time, as shown in FIG. 4, the hub signal is transmitted from the node A in the hub switch 5 to the reception data processing means 10 at a position corresponding to the node B in the terminal switch 12 with a delay of the phase d1. Since the phase signal 3b leads the phase difference D, the clock 8a and the hub signal 9a are synchronized. Received data processing means 1
0 takes in the hub signal 9a at the timing of the clock 8a synchronized with the hub signal 9a, and outputs the hub signal 9a.
Process the data on.

In the first mode, the clock 1a
Becomes the master clock for the PLL circuit 3 to detect the phase difference D. Further, in the second mode, the clock 8a becomes a master clock for performing normal data communication between the hub and the terminal.

Next, the internal structure of the PLL circuit 3 will be described. FIG. 5 is a block diagram showing an internal configuration of the PLL circuit 3. The edge detection circuits 20, 21, the counters 22, 24, 26, 27 and the n-bit register 25 are supplied with a clock φ having a cycle sufficiently smaller than that of the clock 1a output from a means (not shown) for generating a clock. In response to the received clock φ, each of the above blocks operates.

First, the generation of the synchronization signal 3a will be described. First, the edge detection circuit 20 receives the terminal signal 2a and outputs an edge pulse at the rising timing of the terminal signal 2a. The RS-flip-flop circuit (hereinafter referred to as RS-FF) 23 receives the edge pulse and sets the synchronizing signal 3a to the "H" level. Along with that, counter 2
2 starts counting up when the count value is 0,
After a certain period of time, the reset input of RS-FF23
By outputting the "H" level and setting the synchronizing signal 3a to the "L" level, the synchronizing signal 3a having a pulse waveform is generated. When the counter 22 outputs the "H" level, the counter 22 stops counting up and the count value becomes 0. , And the output of the counter 22 is also returned to the “L” level in this way, and the terminal signal 2a
A pulse waveform synchronized with is generated as the synchronization signal 3a.

Next, the detection of the phase difference D will be described.
First, as shown in FIG. 1, the hub switch 5 uses the clock 1
After selecting a, the terminal switch 12 selects the hub signal 9a and puts it in the state of the first mode, the edge detecting circuit 21 receives the clock 1a, and outputs an edge pulse at the rising timing of the clock 1a. The counter 24 receives the edge pulse and starts counting up. Thereafter, the terminal signal 2a is input to the edge detection circuit 20, outputs an edge pulse, and counts the edge pulse by the counter 24.
Received and stopped counting up. The n-bit register 25 receives and stores the count value of the counter 24 at that time. The count value stored in the n-bit register 25 is held as the phase difference D, and even when the state shifts to the second mode, the count value detected in the first mode is held as the phase difference D.

Next, the generation of the phase advance signal 3b will be described. First, the maximum value of the count value of the counter 26 is preset to a value obtained by subtracting 1 from the value obtained by dividing the cycle of the clock 1a by the clock φ. Further, the counter 26 receives the count value which is the phase difference D stored in the n-bit register 25 and sets it as the initial value of the count value. As one specific example, the value obtained by dividing the cycle of the clock 1a by the clock φ is 3 below.
2, that is, the maximum count value of the counter 26 is 31, n
The count value stored in the bit register 25 is 10
The case will be described. First, in the first mode, n
The bit register 25 counts the phase difference D (= 1
0), the hub switch 5
Selects the phase advance signal 3b, the terminal switch 12 selects the signal 11a output by the transmission data processing means 11, and shifts to the second mode. In the second mode, the terminal signal 2
The edge detection circuit 20 receives a, outputs an edge pulse, and the counter 26 receives the edge pulse, and starts counting up from the initial value (= 10). Then, when the count value reaches the maximum value (= 31), the counter 26 becomes "H".
Output level to OUT. RS-FF28 is that
Upon receiving the H "level, the phase advance signal 3b is set to the" H "level. At the same time, the counter 27 starts counting up from the state where the count value is 0, and after a certain period of time, RS-
The "H" level is output to the reset input of the FF 28 to set the phase advance signal 3a to the "L" level. Counter 27 is
When the H "level is output, the count-up is stopped, the count value is returned to 0, and the output of the counter 27 is also returned to the" L "level. Thus, the counter 26 changes from the initial value (= 10) to the maximum value (= 31). The time counting up to is
Referring to, since the time corresponds to the time d3, the phase advance signal 3b that is advanced from the terminal signal 2a by the phase difference D is obtained.

As described above, in this embodiment, the PL
Since the same clock can be used for transmission and reception for normal data communication without requiring the L circuit, the design of the terminal becomes easier than before, and the star communication system becomes inexpensive. Further, in the second mode, since the terminal clock generating means 8 becomes the master clock for normal data communication, the PLL circuit of the hub can generate a phase advance signal which is a signal whose phase advances by the phase difference D. Thus, the terminal can determine the clock for data communication. Therefore, since the terminal determines the so-called data transmission rate, when the terminal is busy with processing other than communication, the terminal can reduce the frequency of the clock output by the clock generation means and reduce the transmission / reception transmission rate. As a result, it is possible to reduce power consumption and traffic control from the terminal side to suppress the data transmission rate from the hub to the terminal.

Embodiment 2 FIG. 6 is a diagram showing a star communication system according to the second embodiment of the present invention. Figure 6
14 is connected to the PLL circuit 3 and is a non-volatile storage means for storing the phase difference D detected by the PLL circuit 3, and other reference numerals correspond to the reference numerals in FIG. Specifically, the storage means 14 is connected to the n-bit register 25 shown in FIG.

Next, the operation will be described. The main operation is similar to that of the first embodiment. First, the hub 10
0 and the first mode is performed only when the first star communication system is started up such as when the terminal 200 is installed. By performing this first mode, the PLL circuit 3 obtains the phase difference D, and the phase difference D is stored in the storage means 14. In detail,
After the n-bit register 25 shown in FIG. 5 stores the count value which is the phase difference D, the storage means 14 receives and stores the count value.

After storing the phase difference D in the storage means 14,
The star type communication system is in the second mode, that is, the hub switch 5 selects the phase advance signal 3b and the terminal switch 1
2 fixes the signal 11a in the selected state. After that, the start-up of the star type communication system starts from the second mode, and the PLL circuit 3 receives the phase difference D from the storage device 14 and generates the phase advance signal 3b. Specifically, the n-bit register 25 shown in FIG. 5 receives the count value stored in the storage means 14, and the n-bit register 25 sets the count value as the phase difference D. Other operations are the same as those in the first embodiment.

As described above, in this embodiment, it is not necessary to perform the mode 1 every time the power is turned on, and the time required to start up the communication system can be shortened.

In the first and second embodiments, the hub 100 may be composed of one block 101.

[Brief description of drawings]

FIG. 1 is a diagram showing a star communication system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a star type communication system according to the first embodiment of the present invention.

FIG. 3 is a diagram showing timing of each signal in the star communication system according to the first embodiment of the present invention.

FIG. 4 is a diagram showing timings of respective signals in the star communication system according to the first embodiment of the present invention.

5 is a block diagram showing an internal configuration of a PLL circuit 3. FIG.

FIG. 6 is a diagram showing a star communication system according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a conventional star communication system.

[Explanation of symbols]

1 hub clock generation means, 2 receivers, 3 PLLs
Circuit, 4 received data processing means, 5 hub switch, 6
Transmission data processing means, 7 driver, 8 terminal clock generation means, 9 receiver, 10 reception data processing means, 11 transmission data processing means, 12 terminal switch,
13 driver, 14 storage means, 20, 21 edge detection circuit, 22 counter, 23 RS-FF, 24
Counter, 25 n-bit register, 26, 27 counter, 28 RS-FF, 100 hub, 101 block, 200 terminal, 300 communication line.

Claims (2)

[Claims] 1. A star communication system for performing communication by transmitting a hub signal generated in a hub to a terminal and transmitting a terminal signal generated in the terminal to the hub, wherein the hub comprises: Hub clock generating means for generating a clock of 1, and a synchronization signal synchronized with the terminal signal and a constant signal from the terminal signal in response to the first clock and the terminal signal transmitted from the terminal to the hub. A PLL circuit that generates a phase advance signal whose phase is advanced by the amount of the phase difference, and receives either the first clock or the phase advance signal and selects either the first clock or the phase advance signal. A hub switch that outputs as a hub synchronization signal; and a first transmission data that receives the hub synchronization signal, processes data to be transmitted to the terminal at the timing of the hub synchronization signal, and outputs the hub signal as the hub signal. A first reception data processing unit that receives the terminal signal and the synchronization signal transmitted by the terminal to the hub, and processes the terminal signal according to the synchronization signal. Terminal clock generation means for generating a second clock, and second transmission data processing means for receiving the second clock and processing and outputting data to be transmitted to the hub at the timing of the second clock. Receiving the output of the second transmission data processing means and the hub signal transmitted to the terminal by the hub, selecting either the output of the second transmission data processing means or the hub signal, A terminal switch for outputting as a terminal signal; the hub signal transmitted to the terminal by the hub; and the second
Second received data processing means for processing the hub signal according to the second clock, the PLL circuit selecting the first clock by the hub switch, A star communication system for detecting the phase difference between the first clock and the terminal signal when the output of the second transmission data processing means is selected by a switch as the constant phase difference. 2. The hub further comprises a non-volatile storage unit that receives the phase difference detected by the PLL circuit and stores the phase difference, and the PLL circuit stores the phase difference in the storage unit. The star communication system according to claim 1, wherein the phase advance signal is generated based on a phase difference.