JPH0438154U - - Google Patents
Info
- Publication number
- JPH0438154U JPH0438154U JP7928990U JP7928990U JPH0438154U JP H0438154 U JPH0438154 U JP H0438154U JP 7928990 U JP7928990 U JP 7928990U JP 7928990 U JP7928990 U JP 7928990U JP H0438154 U JPH0438154 U JP H0438154U
- Authority
- JP
- Japan
- Prior art keywords
- start bit
- reading
- interrupt signal
- received data
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Description
第１図は本考案の構成を示す機能ブロツク図。
第２図は本考案の一実施例の構成を示すブロツク
図。第３図は本考案の一実施例におけるタイマの
構成を示すブロツク図。第４図、第５図、第６図
および第８図は本考案の一実施例の作用の説明に
供するフローチヤート。第７図は本考案の一実施
例の作用の説明に供する受信データの読み取りタ
イミング図。
１……タイマカウンタ、２……割込み信号発生
手段、３……スタートビツト検出手段、４……読
み取り時期決定手段、５……読み取り手段、１１
……マイクロコンピユータ、１８……外部機器。
FIG. 1 is a functional block diagram showing the configuration of the present invention.
FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a timer in an embodiment of the present invention. FIG. 4, FIG. 5, FIG. 6, and FIG. 8 are flowcharts for explaining the operation of one embodiment of the present invention. FIG. 7 is a timing diagram for reading received data to explain the operation of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Timer counter, 2...Interrupt signal generation means, 3...Start bit detection means, 4...Reading timing determining means, 5...Reading means, 11
...Microcomputer, 18...External equipment.
Claims (1)
タイマカウンタの計数値が読め、かつタイマ割込
み信号を出力する１つの割込み信号発生手段と、
受信スタートビツトのエツジを検出するスタート
ビツト検出手段と、スタートビツト検出手段によ
る検出エツジの発生時期におけるタイマカウンタ
の計数値に対応して受信データを読み取り時期を
決定する読み取り時期決定手段と、読み取り時期
決定手段によつて決定された時期に受信データを
読み取る読み取り手段とを備えたことを特徴とす
るシリアル通信による全二重通信方式。 In the full duplex communication method using serial communication,
one interrupt signal generating means that can read the counted value of the timer counter and outputs a timer interrupt signal;
a start bit detection means for detecting an edge of a received start bit; a reading timing determining means for determining when to read received data in accordance with a count value of a timer counter at the time when an edge detected by the start bit detecting means occurs; 1. A full-duplex communication system using serial communication, comprising: reading means for reading received data at a time determined by the determining means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990079289U JP2530040Y2 (en) | 1990-07-27 | 1990-07-27 | Full-duplex communication method by serial communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990079289U JP2530040Y2 (en) | 1990-07-27 | 1990-07-27 | Full-duplex communication method by serial communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0438154U true JPH0438154U (en) | 1992-03-31 |
| JP2530040Y2 JP2530040Y2 (en) | 1997-03-26 |
Family
ID=31623315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990079289U Expired - Lifetime JP2530040Y2 (en) | 1990-07-27 | 1990-07-27 | Full-duplex communication method by serial communication |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2530040Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006352512A (en) * | 2005-06-16 | 2006-12-28 | Nec Engineering Ltd | Data transmission device and method |
| JP2022048317A (en) * | 2019-12-10 | 2022-03-25 | カシオ計算機株式会社 | Electronic apparatus, control method for electronic apparatus, and control program for electronic apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6160037A (en) * | 1984-08-31 | 1986-03-27 | Nec Corp | Two-wire/four-wire signal connecting circuit |
| JPS6420747A (en) * | 1987-07-16 | 1989-01-24 | Nec Corp | Two-wire type full duplex modulator-demodulator |
-
1990
- 1990-07-27 JP JP1990079289U patent/JP2530040Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6160037A (en) * | 1984-08-31 | 1986-03-27 | Nec Corp | Two-wire/four-wire signal connecting circuit |
| JPS6420747A (en) * | 1987-07-16 | 1989-01-24 | Nec Corp | Two-wire type full duplex modulator-demodulator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006352512A (en) * | 2005-06-16 | 2006-12-28 | Nec Engineering Ltd | Data transmission device and method |
| JP4632871B2 (en) * | 2005-06-16 | 2011-02-16 | Ｎｅｃエンジニアリング株式会社 | Data transmission apparatus and transmission method |
| JP2022048317A (en) * | 2019-12-10 | 2022-03-25 | カシオ計算機株式会社 | Electronic apparatus, control method for electronic apparatus, and control program for electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2530040Y2 (en) | 1997-03-26 |
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